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High frequency CMOS amplifier with improved linearity

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In this paper, a novel amplifier linearisation technique based on the negative impedance compensation is presented. As demonstrated by using Volterra model, the proposed technique is suitable for linearising amplifiers with low open-loop gain, which
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  Published in IET Circuits, Devices & SystemsReceived on 7th March 2013Revised on 17th January 2014Accepted on 22nd January 2014doi:10.1049/iet-cds.2013.0327 ISSN 1751-858X High frequency CMOS amplifier with improvedlinearity M. Tanseer Ali  1 , Ruiheng Wu  1 , Luhong Mao  2  , Peter Callaghan  1 , Predrag Rapajic  1 1 School of Engineering, University of Greenwich, Chatham Maritime, Kent ME4 4TB, UK  2  School of Electronic Information Engineering, Tianjin University, Tianjin 300072, People  ’    s Republic of China E-mail: r.wu@gre.ac.uk  Abstract:  In this paper, a novel ampli fi er linearisation technique based on the negative impedance compensation is presented. Asdemonstrated by using Volterra model, the proposed technique is suitable for linearising ampli fi ers with low open-loop gain,which is appropriate for RF/microwave applications. A single-chip CMOS ampli fi er has been designed using the proposed method, and the simulation results show that high gain accuracy (improved by 38%) and high linearity (IMD 3  improved by14 dB, OIP 3  improved by 11 dB and adjacent channel power ratio (ACPR) improved by 44% for CDMA signal) can be achieved. 1 Introduction The rapid and high growth in wireless technology has placed an emergent use of different modulations techniques such asOFDM, CDMA, QAM etc. These modulations require highlinearity in terms of spectrum leakage and intermodulationdistortion (IMD). It is important and pressing to designmonolithic high frequency ampli fi ers with high gainaccuracy, good linearity and wide bandwidth in moderncommunication circuits and systems. Some new methodshave been reported in recent years to achieve different levels of linearity by using special predistortion [1 – 8],compensating pre –  post-distortion effect [9, 10] or harmonic/  intermodulation injection [11 – 16]. These methods focus onreducing the distortion at the source end, making themmore ef  fi cient than the traditional linearisation techniques.However, most existing techniques usually require complexcircuitry, which is dif  fi cult for practical realisation,especially for monolithic design. In addition, some methodsmay degrade the level of linearity and ef  fi ciency whenworking at high operating frequencies. Recently, in order todesign highly linear fully integrated ampli fi er a great dealof attention has been directed towards to the designmethods employing special transistor arrangement to provide active auxiliary compensation [17 – 21]. In this paper, a novel highly linear ampli fi er design method based the negative impedance compensation [22, 23] is applied to a practical circuit design that can be realised in current RFCMOS technology. As demonstrated by using the Volterramodel, the speci fi c feedback structure of the proposed linearisation method can effectively improve gain accuracy, bandwidth and linearity. Therefore, the technique isexpected to overcome the limitations of some traditionaltechniques in which the linearity is improved by trading off the gain and bandwidth. Also, the proposed method isappropriate for single-chip design as the main and auxiliaryampli fi ers can be designed using a similar structure. As can be seen from a designed ampli fi er in Section 5, compared with the traditional methods a high precision auxiliaryampli fi er is not needed, instead a single auxiliary ampli fi er is adequate for required linearisation. Finally, the proposed method is particularly suitable for linearisation of ampli fi erswith low open-loop gain, a good feature for RF/microwaveapplications. 2 Volterra model of feedback amplifier All ampli fi ers possess the property of distorting the signalsthey are required to amplify. The existence of distortion iscaused by the non-linearity of the ampli fi ers. The harmoniccontents and the intermodulation products of output signalgive measure of the level of non-linearity. 2.1 Feedback topology and its Volterra model  An ampli fi er with negative feedback is shown in Fig. 1. Asdiscussed in [24], the ampli fi er con fi guration can be divided into a linear and a non-linear part as represented by the block diagram shown in Fig. 2. The purpose of our researchis to design a linearisation technique without changing theinternal con fi guration of the main ampli fi er. Therefore  A v  1 (  s ) in Fig. 2 is considered as the only non-linear part of the circuit where any non-linear ampli fi er can be used. Theoperator   H   and   F   are the representation of the basicampli fi er and the linear feedback network, respectively,whereas  Q  is the overall representation of the non-linear system.According to Volterra series the output of a non-linear system can be modelled as sum of the responses of theoperators of the  fi rst order, the second order, the third order and so on. Every operator is described either in the time www.ietdl.org IET Circuits Devices Syst. , pp. 1 – 9doi:10.1049/iet-cds.2013.03271 & The Institution of Engineering and Technology 2014  domain or frequency domain with a kind of transfer functioncalled Volterra Kernels. Following the model shown in Fig. 2,the Volterra kernels can be derived as described in [24]. Sincethe proposed technique can be implemented with any weaklynon-linear ampli fi er, therefore the model has been modi fi ed  by considering the ampli fi er as single block   A v  1  instead of splitting it into two or three stages. The basic ampli fi er  ’ skernel transfer functions are  H  1 (  s 1 ) =  A v 1 (  s 1 )  R G   R  F   R G  +  R  F  (1)  H  2 (  s 1 ,  s 2 ) =  A v 1 (  s 1 )  A v 1 (  s 2 )  R G   R  F   R G  +  R  F    2 (2)  H  3 (  s 1 ,  s 2 ,  s 3 ) =  A v 1 (  s 1 )  A v 1 (  s 2 )  A v 1 (  s 3 )  R G   R  F   R G  +  R  F    3 (3)and the kernel transfer function of the feedback loop (  F  ) will be  F  1 (  s 1 ) =− 1  R  F  (4)Since the feedback network has been considered to be linear,the second-order and third-order feedback kernels will be  F  1 (  s 1 ,  s 2 ) =  F  1 (  s 1 ,  s 2 ,  s 3 ) = 0 (5)The gain reduction factor will be  R (  s 1 ) = 11 +  H  1 (  s 1 )  F  1 (  s 1 ) (6)For large loop gain, (6) can be reduced to  R (  s 1 ) ≃ 1  H  1 (  s 1 )  F  1 (  s 1 ) (7)Therefore, the  fi rst, second and third-order transfer functionof the overall system can be calculated as Q 1 (  s 1 ) =  H  1 (  s 1 ) ·  R (  s 1 ) =−  R  F   (8) Q 2 (  s 1 ,  s 2 ) =  R (  s 1 )  R (  s 2 )  R (  s 1 +  s 2 )  H  2 (  s 1 ,  s 2 ) (9)(see (10))Substituting for the values of the kernel transfer functionsfrom (2) and (7) in (9) yields Q 2 (  s 1 ,  s 2 ) =− (  R G  +  R  F  )  R 2  F   A v 1 (  s 1 +  s 2 )  R G  (11)Similarly, substituting for the values of the kernel transfer functions from (1) – (3) and (7) in (10) gives Q 3 (  s 1 ,  s 2 ,  s 3 ) =− (  R G  +  R  F  )  R 3  F   A v 1 (  s 1 +  s 2 +  s 3 )  R G  (12) 2.2 Harmonic distortion  Typical non-linearity analysis of an ampli fi er requiresmeasuring the harmonics at the output produced by a singletone input. For single tone input, the fundamentalcomponent of the output voltage can be considered as V  out1  =  I  in  Q 1 (  j  v  1 )   (13)where  I  in = V  in /   R G  , and we assume that the input current and voltage are i in  =  I  in  sin( v  1 t  ) (14) v in  = V  in  sin( v  1 t  ) (15)The second and third harmonic of the output voltage can befound as V  out2  = 12  I  2in  Q 2 (  j  v  1 ,  j  v  1 )   (16) V  out3  = 14  I  3in  Q 3 (  j  v  1 ,  j  v  1 ,  j  v  1 )   (17)Using (16) and (17) the second and third-order harmonic Fig. 1  Ampli   fi er with negative feedback  Fig. 2  Volterra model of the feedback ampli   fi er in Fig. 1 Q 3 (  s 1 ,  s 2 ,  s 3 )  =  R (  s 1 )  R (  s 2 )  R (  s 3 )  H  3 (  s 1 ,  s 2 ,  s 3 ) − 2  H  2 (  s 1 ,  s 2 )  H  2 (  s 3 ,  s 1 +  s 2 )  H  1 (  s 1 +  s 2 )    R (  s 1 +  s 2 +  s 3 ) (10) www.ietdl.org 2 & The Institution of Engineering and Technology 2014 IET Circuits Devices Syst. , pp. 1 – 9doi:10.1049/iet-cds.2013.0327  distortion of the output can be determined [24]HD 2  f    = 12  I  in Q 2 (  j  v  1 ,  j  v  1 ) Q 1 (  j  v  1 )  (18)HD 3  f    = 14  I  2in Q 3 (  j  v  1 ,  j  v  1 ,  j  v  1 ) Q 1 (  j  v  1 )  (19)Using the derived Volterra models of the transfer functions in(8), (11) and (12) the second and third-order harmonicdistortion can be determined asHD 2  f    = 12 V  in 1  A v 1 (2  j  v  1 )  (  R G  +  R  F  )  R  F   R 2 G  (20)HD 3  f    = 14 V  2in 1  A v 1 (3  j  v  1 )  (  R G  +  R  F  )  R 2  F   R 3 G  (21) 2.3 Intermodulation distortion  The two-tone test is the most widely accepted method for measuring IMD, where the two-tone input signals are bothset to the same amplitude at two different frequencies as v in ( t  ) = V  in  sin( v  1 t  ) + V  in  sin( v  2 t  ) (22)Using the above derived Volterra model and the two-tonesignals in (22), the third-order IMD can be measured as [24]IMD 3  f    = 34  I  2in Q 3 (  j  v  1 ,  −  j  v  2 ,  −  j  v  2 ) Q 1 (  j  v  1 )  = 34 V  2in 1  A v 1 (  j  v  1 − 2  j  v  2 )  (  R G  +  R  F  )  R 2  F   R 3 G  (23) 3 Negative impedance compensation One of the main focuses of the proposed technique is tolinearise a high frequency ampli fi er with low open-loopgain. The analysis and the non-linear model introduced inlast section show that the linearity could be improved bytuning the value of the passive components. However, thegain may be compromised. One alternative solution is tointroduce an additional correction signal using an auxiliarycircuit so that the linearity can be improved without losingthe gain.The linear ampli fi er design used in this paper is based onthe negative impedance compensation presented in [22, 23]. As shown in Fig. 3 a , the key point of the proposed method is adding a negative impedance to the input terminal of theampli fi er to carry out distortion correction for the output signal. As proved in [22, 23], the value of the negative impedance can be calculated as  R  N   =−  R G  ||  R  F   =−  R G   R  F   R G  +  R  F  (24)Fig. 3 b  shows the Thevenin ’ s equivalent circuit of Fig. 3 a ,where  R ′ G   =  R G  //  R  N  . The Volterra model of the second and third-order harmonic distortion with the compensationcan be determined asHD 2  f    with = 12 V  ′ in 1  A v 1 (2  j  v  1 )  (  R ′ G  +  R  F  )  R  F   R ′ 2 G  (25)HD 3  f    with = 14 V  ′ 2in 1  A v 1 (3  j  v  1 )  (  R ′ G  +  R  F  )  R  F  2  R ′ 3 G  (26)Similarly, the Volterra model of the third-order IMD based onthe two-tone test can be obtained asIMD 3  f    with = 34 V  ′ 2in 1  A v 1 (  j  v  1 − 2  j  v  2 )  (  R ′ G  +  R  F  )  R 2  F   R ′ 3 G  (27)where  V  ′ in  is the Thevenin ’ s equivalent input of Fig. 3 a .As can be seen, when the value of   R ′ G   in (25), (26) and (27)is replaced by  R G  //   R  N  ,  R ′ G  +  R  F    = 0, which will result inHD 2   f   | with  =0, HD 3   f   | with  = 0 and IMD 3   f   | with  = 0. That is:theoretically, the second and third-order harmonic distortionas well as the IMD can be cancelled with the compensationtechnique.As shown in (7) and (8), some of the theoretical results arederived based on an assumption that the ampli fi er has a largeloop gain, this may not always be true in practical design.However, as shown by the example in [22] and thesimulation results in this paper, the proposed technique hasquite wide compensation range in terms of the negativeimpedance even when the loop gain is low. In addition, inorder to obtain optimal linearisation result, some factorssuch as component tolerance and complex input impedanceof main ampli fi er may need to be considered in practicaldesign, and, consequently, the value of   R  N   could bedifferent from that in (24). Fig. 3  Feedback ampli   fi er with compensation a  Ampli fi er with a negative impedance connected to the input terminal b  Equivalent circuit of (a) www.ietdl.org IET Circuits Devices Syst. , pp. 1 – 9doi:10.1049/iet-cds.2013.03273 & The Institution of Engineering and Technology 2014  4 Realisation of the negative impedance As can be seen from above analysis, the negative impedance plays a key role in the linearisation. Practically, there areseveral methods to realise a negative impedance. Fig. 4shows the negative impedance realisation in the proposed method, where the auxiliary ampli fi er ( α  ) acts as anattenuator to provide 2 V   N   ( V   N   is the voltage at the input terminal of the main ampli fi er) so that the correctionimpedance connected to the main ampli fi er is Z   N   = V   N   − 2 V   N  i  R n =−  R n  =−  R G  ||  R  F   (28)where  i  Rn  is the current going through the compensatingresistance  R n .In Fig. 4, the attenuation factor   α   of the auxiliary ampli fi er can be determined as follows.As the output of attenuator is a V  o  = 2 V   N   (29)where  V  o  is the output voltage of the main ampli fi er.Hence a = 2 V   N  V  o = 2 V  o / V   N  = 2  A  (30)where  A  is the open-loop gain of ampli fi er.In Fig. 4, the auxiliary ampli fi er can be built around thesame structure as the main ampli fi er, so the complete circuit con fi guration will be easy to implement. Since the sameCMOS transistor con fi gurations can be used, the completecircuit is amendable to build in single-chip solutionincluding the on-chip linearisation. 5 Single-chip amplifier design and test 5.1 Circuit design  To demonstrate the proposed method a double gated CMOSampli fi er [21] has been utilised. Fig. 5 shows the designed  CMOS ampli fi er, where the upper part consisting of thetransistors M 1 , M 2  and M 3  is the main ampli fi er to be Fig. 4  Realisation of the negative impedance compensation Fig. 5  CMOS ampli   fi er with negative impedance compensation www.ietdl.org 4 & The Institution of Engineering and Technology 2014 IET Circuits Devices Syst. , pp. 1 – 9doi:10.1049/iet-cds.2013.0327  linearised, and the auxiliary ampli fi er implemented with asingle transistor M 4  is used to carry out the compensationfor the main ampli fi er. As shown in [22, 23], generally, when using the negative impedance compensation theauxiliary ampli fi er may need not be highly linear as it is part of the negative impedance circuit and handles smallsignal. This technique compares favourably with other two-path linearisation methods where, in general, thelinearising signal path handles larger signal levels and therefore must itself be highly linear. Also, the auxiliarycircuit can perform satisfactory compensation in a largeregion with different   Z   N  .The ampli fi er shown in Fig. 5 is designed to operate at 2.2GHz so that it can be implemented with CDMA modulated signal and the level of linearity can be analysed with practical scenario. The  fi nal ampli fi er provided a smallopen-loop gain which further reduced after the feedback effect. Therefore an additional ampli fi er was required toenhance the open-loop gain of the ampli fi er.In Fig. 5, in order to realise the negative impedance, theauxiliary ampli fi er has been connected between the output and the compensating impedance,  Z   N  , which has beenimplemented with single poly resistor model for sake of simplicity of the design. The auxiliary ampli fi er consists of asingle transistor M 4 , which is biased with  V  G3  and theattenuation of the ampli fi er is set following the similar method discussed in Section 4 by adjusting the value of   R A1 and   R A2 . In order to improve the ef  fi ciency of the auxiliaryampli fi er the drain is connected to  V  DD  with inductance  L A .The parameters and performance characteristics of theCMOS ampli fi er are modelled by BSIM3v3.2 [25], and the fi nal design parameters are shown in Table 1.The parasitic effects of the circuit effectively alter the biascondition for the transistors, in addition to that, the drain-gateDC voltage level has to be limited under recommended level.Therefore the values of the spiral inductor model and themetal insulator metal (MIM) capacitor model used in thedesign have to be tailored (different from the ideal values)to restore the biasing point. Tables 2 and  3 show the  parameters for the inductors and capacitors used in theampli fi er design.In addition, the speci fi cation of the resistive component (non-salicided poly resistor model) also need to be tailored to achieve the optimal performance. Table 4 shows the parameters of these resistors.In this context a simple L-section matching network has been utilised. Since the passive device models availablefrom United Microelectronics Corporation (UMC) foundrydesign kit (FDK) have a limited range of values, therequired impedance cannot be matched in single stage. The fi nal matched input impedance is (52+ j41) Ω  at anoperating frequency of 2.2 GHz. The transformed output impedance of the developed ampli fi er has been realised as(51.72 +j3.93) Ω  at 2.2 GHz by using a single stageL-section matching network.The single-chip design, simulation and tape-out have been performed for the ampli fi er in Fig. 5 by using Virtuoso ® SpectreRF analogue environment in Cadence, where the RFmodels in UMC FDK library have been used. TheMOSFET transistors used from the FDK models aredeveloped on BSIM3v3.3 models [25].Finally, utilising the associated layer de fi nitions and layout PCells of the FDK models, the layout has been developed asshown in Fig. 6 using 0.18  µ m CMOS technology. Thedeveloped layout has about 1349.5 µm ×2382.5 µm of chiparea. 5.2 Circuit simulation  For optimal performance the closed-loop power gain of thefeedback con fi guration has been set as 15(11.8 dB). Thesimulation results in Fig. 7 show that, when the operatingfrequency is 2 GHz, the gain of the designed ampli fi er without linearisation is 7.5 dB while the gain withlinearisation can achieve up to 10.4 dB, the gain accuracyhas been improved by more than 38%.As shown in Fig. 8, when simulated with two tones at 2and 2.01 GHz, the srcinal ampli fi er exhibits OIP 3  at 1.29dBm. However, OIP 3  of the designed ampli fi er with thenegative impedance linearisation can be as high as 12.24dBm, which reveals a dramatic improvement of linearity asanticipated by the theoretical analysis. In order to test the practical performance of the designed ampli fi er the post layout simulations have been performed, which has lessthan 5% reductions in power gain, but still show signi fi cant improvement in both gain accuracy and linearity. Table 1  Transistor parameters for the designed amplifierProcess Transistor Numberof fingerFingerwidth,µmTotalwidth,µmLength,µm1.8 VmodelM 1  9 5 45 0.18M 2  9 5 45 0.18M 3  11 5 55 0.18M 4  5 5 25 0.18 Table 2  Spiral inductance parameters of the designedamplifierComponent Diameter,µmWidth,µmTurnnumberEffectiveinductance, nH L S  173 6 5.5 10.0 L D1  210 6 5.5 12.4 L D2  210 6 5.5 12.4 L D3  173 6 5.5 10.0 L A  210 6 5.5 12.4 Table 3  MIM capacitor model parameters of the designedamplifierComponent Width,µmLength,µmEffective capacitance,pF C  S  28 28 0.8 C  1  40 40 1.6 C  2  58 58 3.4 Table 4  Specifications of the poly resistors in the amplifierdesignComponent Width, µm Length, µm Effective resistance, k Ω R  S  1 1.6 1.5 R  F  1 2.9 3.0 R  G1  1 2.0 2.0 R  G2  1 2.0 2.0 R  N  1 1.1 1.0 R  A1  1 16.8 18.0 R  A2  1 1.1 1.0 R  A3  1 1.1 1.0 www.ietdl.org IET Circuits Devices Syst. , pp. 1 – 9doi:10.1049/iet-cds.2013.03275 & The Institution of Engineering and Technology 2014
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