Optimization: MVSIS V/s AIG Rewriting (ABC)

For the optimization of given network, VHDL /Verilog code convert into BLIF / BLIF_MV (Berkeley Logic Interchange Format /Berkeley Logic Interchange Format for multi-valued network ) format with the help of VIS / Vl2mv tool of Berkeley. In this paper, we optimize on a number of standard industrial benchmark circuit by MVSIS and ABC tool. After optimization here used some technology mapping, then compare the result. Here we try to find which tool give optimal result of optimization.
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Transcript IJEEE, Vol. 1, Issue 1 (Jan-Feb 2014) MVSIS V/ Deptt. OfElectronic  Abstract- For the optimization ofgi  /Verilog code convert into BLIF / Logic Interchange Format/Berkeley Format for multi-valuednetwork) for VIS / Vl2mv tool of Berkeley.In this p a number ofstandardindustrialbe MVSIS and ABC tool. After optimiza technology mapping, then compare th to find which tool give optimal result o  Index Terms- And-Inverter graph ( Graph (DAG),Hardware Descriptio VHSIC Hardware Description Languag I. INTRODUCTI Optimization of binaryormulti-v using logic synthesis play an import network system[1]. Figure-1: Design Flow   Network Toplogy Readi(VHDL/ Verilog-BV/MBLIF / BLIF_MV Conver(VIs / Vl2mv)Technology Independent Opti(SIS / MVSIS / ABC)Application of Mapping Alg(SIS / MVSIS / ABC)Result Analysis International Journal of Electrical e-ISS PTIMIZATION:S AIG REWRITING Manish Kumar Goyal  s Engineering,Govt. Polytechnic College,Alwar, Raj  en network, VHDL LIF_MV(Berkeley Logic Interchange mat with the help of  aper,we optimize on nchmark circuit by tion here used some result. Here we try foptimization.   AIG),Direct Acyclic Language (HDL), e (VHDL) N  aluedlogic networks ant role ina digital Logic synthesis is derived by compiling HD technology mapping perfor programmable devices. Logi hardware emulation,design c synthesis, and fast preproc equivalence checking[2]. Fi optimize result by MVSIS an II. MVSISis a sequel progr technology independent trans well as sequential logic syste variables can be multi-value MVSIS input formats can be1.PLA or BLIF: For Binary 2.BLIF-MV: For Multi-valu And for FSMs and finite available1.Using BLIF/BLIF- MV fol 2.Using modified KISS2 fo3.Using modified BLIF-MV To analyze the perf applied over 15combinationa MVSISscript logic synthes optimization steps i.e.  SWE   nodes),  ELIMINATE and better logic boundaries),  FA  shared logic boundary FULL_SIMPLIFY  (For representation).[3]In the Table-1, th standardcombinationalMC seven columns show thesta before applying the standard of primary inputs; PO is t while Lits indicate the literal shows, the reduced number and literal(ff) after run MVSI   ng V) sion ization rithm  & Electronics Engineering  31  : 1694-2310|p-ISSN: 1694-2426  (ABC)   sthan, India used on a network which is s, VHDL or Verilog. Then med for standard cell or c synthesis is also fruitful for omplexity estimation, software essing of the circuits before ure-1 shows the process to get d ABC tool. VSIS  am modeled of SIS. MVSIS is formation of combinational as m. It works on is such that all , each with its own range[7]. functions and networks ed functions and networks automata three options are  lowed by “ stg_extract  ”  mat format ormance of this tool, script is l MCNC benchmark circuit.In is is a sequence of applying   EP (For removing redundant  ESUBSTITUTE  (For finding  T_EXTRACT  (For discovering and  SIMPLIFY and   simplifying the node first column shows the15C benchmark circuit[4]. Next tics of the benchmark circuit script. Here, PI is the number e number of primary output, s. The next section of the table of node, level, cubes, literals S (script) over the benchmark.  International Journal of Electrical & Electronics Engineering  32 TABLE-1STATICS OF BENCHMARK CIRCUIT BEFORE AND AFTER APPLYING THE MVSISscript Bench-MarkCircuitCircuit Statics After Run MVSIS ( script)PI PO Node Level Cubes Lits Lits(ff) Node Level Cubes Lits Lits(ff) Duke2222938585909929923628772898890Rd848449598941442144249510111512781249Misex225181236134246246835156189186B1215976991214186018601107229279269Cordic232207912328349694969150013341441633909Pdc16402326174203825973643528147821100469140Spla1646223718412879617034342413739391738578C4323673552937356756717319341442390C13554132949449491467146722010428684678C19083325798557981245124527418566795771T48116110751115552673267378311194523142142B9412127520351408408986175220204Dalu751626095935954541454174315150719621805Des256245226310395789918991382312775898649453K245453994152131763176136810285034093366 TABLE-2DEGREE OF REDUCTION IN NODE AND LITERAL BenchMarkCircuitCircuit Statics AfterMVSIS (Script)Degree of reductionNode Literal Node Literal Node Literal Duke23859923628980.0600.095Rd844951442495127800.114Misex2123246831890.3250.231B1276918601102790.8570.850Cordic20794969150041630.2780.162Pdc23268259352810046(-)0.517(-)0.216Spla2237796134249173(-)0.531(-)0.152C4323555671734420.5130.220C135594914672206840.7680.534C190879812452747950.6570.386T4811075267378323140.2720.134B9275408982200.6440.461Dalu2609454174319620.7150.562Des2263899138239864(-)0.689(-)0.097K2399317613683409(-)2.429(-)0.073Table-2 shows the degree of reduction in benchmark circuit. Here B12 circuit have maximum degree of reductionin node as well as literal is 0.857 and 0.850 respectively. Insome of the benchmarks, i.e. PDC, SPLA, DES and K2,number of node and literals areincreased, but area is reduceas shown in the Table-3.Table-3 shows the degree of areareduction and delay reduction when benchmark circuitsmapped with mcnc.genlib. And, also show areaoptimization with LUT (#K=5).  www.ijeee-apm.comInternational Journal of Electrical & Electronics Engineering  33 TABLE-3ANALYSIS OF AREA AND DELAY BEFORE AND AFTER OPTIMIZATION Becnch-MarkCircuitMapping with mcnc.genlib Mapping with LUT #k=5Before MVSISscriptAfter MVSISscriptDegree of AreaReductionDelayReductionArea BeforeoptimizationArea AfteroptimizationDegree of reductionArea Delay Area Delay Duke29789.38969.30.0840.02202070.059Rd84143710.7124911.20.131(-)0.52752410.124Misex22056.21866.60.093(-)0.442340.190B12150110.42708.40.8202.0299840.719Cordic638414.3391815.50.386(-)1.26475510.148Pdc1020917919316.70.1000.3182416390.101Spla953416859915.90.0980.1183915830.139C43238019.939421.8(-)0.037(-)1.980510.363C135581615.678815.90.034(-)0.368680.0C190885224.1844230.0091.11141070.061T481252413.3214713.30.1490.04103430.163B92297.22056.70.1050.542400.048Dalu282824.61847180.3476.63822760.277Des1136211.6956213.70.1582.1149113320.107K2364611.8340912.10.065(-)0.37226960.036 III. AIG REWRITING (ABC) An And-Inverter graph (AIG)is a direct acyclic graph(DAG). In which node has either 0 or 2 incoming edges. If anode will have no edge then it will primary input (PI) or if node has twoinput edges then it will two-input AND gate.An edge become a normal input or complement of input.Some node will primary output (PO).Another logicsynthesis tool is ABC. In which And-Inverter Graphs(AIGs) can be rewrite for given network. Rewriting is a fastgreedy algorithm[2].This is used for minimizing the AIGsize by iteratively selecting AIG sub-graphs rooted at a nodeand replacing them with smaller pre-computed sub-graphs,while preserving the functionality of the root node.rewriting algorithm is developed with following features:1.Using 4-feasible cuts instead of two-level sub-graphs.2.Restricting rewriting to preserve the number of logiclevels.3.Developing several variations of AIG rewriting to4.Selectively collapse and refactor larger sub-graphs.5.Balance AIG using algebraic tree height reductionIn theAIG rewriting, thenodes arevisited in atopological order. For each 4-input cut of a node, all pre-computed sub-graphs of its NPN class are considered.Logicsharing between the new sub-graphand nodes already in thenetwork is determined. First old sub-graph isdereferenceand thenumber of nodes, whose reference counts became 0,is returned[6].These nodes will be removed if the old sub-graph is replaced. Next, a new sub-graph is added whilecounting the number of new node and the node whosereference count went from 0 to a positive value.Thesenodeswilladd. The difference of the counter is the gain inthe number of nodes if the replacement is done. The newnode isde-referencedand the old node is referenced toreturn the AIG to its srcinal state.After trying all availablesub-graphsfor the given node,the one that leads to the largest improvement at a node isused.If there is no improvement and “Zero -Costreplaceme nt” is enabled, a new sub -graph that does notincrease the number of nodes is used.Table-4 shows thereduction in node with every iteration. Table-5 shows thereduction in area and delay when technology mapped bymcnc.genlib. TABLE-4REWRITING PERFORMANCE OF MCNC BENCH MARK BenchMarkCircuitFirst Iteration (rwz) Second Iteration (rwz) Third Iteration (rwz)NodeRewrittenGain % Gain NodeRewrittenGain % Gain NodeRewrittenGain %Gain Duke22745710.59221306.24203194.21Rd84224719.97213304.68201223.60Misex2451210.173643.773610.98B1263224625.1340111415.553426710.82Cordic1164178564.3731012512.65242698.00Pdc23972084.1620822084.3419301162.53Spla21951653.4619042194.7617671092.49C432993114.6265147.734895.39C135522010019.5359184.375400.0C1908125317.547482.117020.54  International Journal of Electrical & Electronics Engineering  34 T48152151437.1126212113.89193557.33B9362823.142577.531922.33Dalu71457132.91311534.55249141.26Des200399320.9911282456.55842471.35K2147045820.0110551045.68921382.20 TABLE-5ANALYSIS OF ABC WITH MCNC.GENLIB BenchMark CircuitBefore ABC script.scrAfter ABC script.scrDegree of reductionNodeNetAreaDelayNodeNetAreaDelayNodeNetAreaDelayDuke23929599669.23538308359.30.0990.1350.136(-)0.1Rd845111449145210.74971237123911.30.0270.1460.147(-)1.6Misex2831951956.2801801805.80.0360.0770.0770.4B126541786178610.43871011101110.20.4080.4340.4340.2Cordic19706464646514.311392982299114.70.4220.5390.537(-)0.4Pdc38259558959217.233898665869416.40.1140.0930.0940.8Spla37129221925016.232698175820115.90.1190.1130.1130.3C43218540440521.915233834820.50.1780.1630.1411.4C135521848081615.620043176914.10.0830.1020.0581.5C190829667790224.528864886324.30.0270.0430.0430.2T4819202558256613.37531993199913.60.1820.2210.221(-)0.3B9992162177.8871811827.00.1210.1620.1610.8Dalu10892578280824.68481980208020.80.2210.2320.2593.6Des36879423971812.732438210851812.20.1200.1290.1230.5K214113536358112.412362997305312.10.1240.1520.1470.3 IV. ANALYSIS OF OPTIMIZATION This section compares AIG rewriting in ABC withlogic synthesis in MVSIS on MCNC benchmark. Table-6shows that Node reduction with MVSIS (script) and ABC(resyn2), and also shows that area and delay reduction of mapping of optimizebenchmark, which shows itis better inABC. ABC (resyn2) based on area optimization under delayconstraints. Therefore in some benchmarks delay isincreased as compare to MVSIS (script). TABLE-6COMPARISON BETWEEN MVSIS AND ABC Bench Mark CircuitDegree of Reduction in MVSISDegree ofReduction in ABCNodeAreaDelayNodeAreaDelayDuke20.0600.0840.00.0990.136(-)0.1Rd8400.131(-)0.50.0270.147(-)1.6Misex20.3250.093(-)0.40.0360.0770.4B120.8570.8202.00.4080.4340.2Cordic0.2780.386(-)1.20.4220.537(-)0.4Pdc(-)0.5170.1000.30.1140.0940.8Spla(-)0.5310.0980.10.1190.1130.3C4320.513(-)0.037(-)1.90.1780.1411.4C13550.7680.034(-)0.30.0830.0581.5C19080.6570.0091.10.0270.0430.2T4810.2720.1490.00.1820.221(-)0.3B90.6440.1050.50.1210.1610.8Dalu0.7150.3476.60.2210.2593.6Des(-)0.6890.1582.10.1200.1230.5K2(-)2.4290.065(-)0.30.1240.1470.3 V. CONCLUSION AIG rewriting is an innovative technique forcombinational logic synthesis. This experiment shows thatAIG rewriting often leads to quality comparable or betterthan those afforded by the logic synthesis script in MVSIS.The extreme speed and good quality of the proposedalgorithm might make the new flow useful in a variety of applications such as hardwareemulation, estimation of design complexity, and equivalence checking. REFERENCE [1]. ‘Optimization of Multi -Valued Multi- Level Networks’ -M.Gao, J-H.Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa and R.Brayton; 32 nd IEE International Symposium on Multiple-Valued Logic (ISMVL’02
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