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  See discussions, stats, and author profiles for this publication at: A Framework for Object-Oriented EmbeddedSystem Development Based on OO-ASIPs.  Article   in  Journal of Circuits System and Computers · December 2008 DOI: 10.1142/S0218126608004812 · Source: DBLP CITATION 1 READS 58 4 authors:Some of the authors of this publication are also working on these related projects: HW-SW Co-design for Apache Storm Throughput Enhancement   View projectRenewable Energies for Green Data Centers   View projectNaser MohammadzadehShahed University 21   PUBLICATIONS   66   CITATIONS   SEE PROFILE Shaahin HessabiSharif University of Technology 110   PUBLICATIONS   413   CITATIONS   SEE PROFILE Maziar GoudarziSharif University of Technology 94   PUBLICATIONS   243   CITATIONS   SEE PROFILE Mahdi MalakiShahid Beheshti University 9   PUBLICATIONS   71   CITATIONS   SEE PROFILE All content following this page was uploaded by Mahdi Malaki on 06 January 2017. The user has requested enhancement of the downloaded file. All in-text references underlined in blue are added to the srcinal documentand are linked to publications on ResearchGate, letting you access and read them immediately.  February 6, 2009 10:23 WSPC/123-JCSC 00481 Journal of Circuits, Systems, and ComputersVol. 17, No. 6 (2008) 973–993c   World Scientific Publishing Company A FRAMEWORK FOR OBJECT-ORIENTED EMBEDDEDSYSTEM DEVELOPMENT BASED ON OO-ASIPS NASER MOHAMMADZADEH ∗ and SHAAHIN HESSABI † Department of Computer Engineering,Sharif University of Technology,Azadi Ave., Tehran, Iran  ∗  †  MAZIAR GOUDARZI System LSI Research Center, Kyushu University,Fukuoka, Japan MAHDI MALAKI Department of Computer Engineering,Sharif University of Technology,Azadi Ave, Tehran, Iran  Revised 15 April 2008The growing complexity of today’s embedded systems demands new methodologiesand tools to manage the problems of analysis, design, implementation, and validationof complex-embedded systems. Focusing on this issue, this paper describes a designand implementation toolset using our ODYSSEY methodology, which advocates object-oriented (OO) modeling of embedded systems and its ASIP-based implementation. Theproposed approach promotes a smooth transition from high-level object-oriented spec-ification to the final embedded system, which is composed of hardware and softwarecomponents. The transition from higher to lower abstraction levels is facilitated by theuse of our GUI, which supports the intermediate steps of the design and implemen-tation process. In order to illustrate the proposed approach and related toolset, weapply this top-down design and implementation framework to real-world embedded sys-tems, namely JPEG codec and Motion JPEG codec. Experimental results show thatthe developed tool remarkably decreases the design and verification time with modestperformance penalty. Keywords : Embedded systems; object-oriented design; design automation tool; polymor-phism; Application-Specific Instruction Processor (ASIP).973  February 6, 2009 10:23 WSPC/123-JCSC 00481 974  N. Mohammadzadeh et al. 1. Introduction Embedded systems are usually implemented as combinations of hardware with gen-eral purpose computational capabilities and more dedicated modules. Together,they perform a function carefully partitioned in software and hardware to obtainthe optimum trade-off between the various quality metrics. This type of imple-mentations has become increasingly popular as advances in integrated-circuittechnology and processor architectures allow flexible computational parts and high-performance modules integrated on a single chip.Despite advances in manufacturing technology, design-technology lags farbehind; it is nowadays a common practice that all system-level decisions are taken ad hoc  in the beginning of the design process. Months of efforts are then investedin realizing them, often manually hand-crafting the embedded software in assemblylanguage. Since there is usually no time left for the second try, many of these deci-sions have to be conservative to guarantee the system correctness. Also, the designreuse is limited, which results in longer time-to-market times. Clearly, this leads toless market-competitive products.The design automation for embedded systems is becoming a “must”. Whatis needed is an interactive environment that supports the designer, not only intransforming a high-level specification into a suitable implementation, but also inreusing the already implemented applications. The environment should allow fastexperimentation with different architectural options and relieve the designer fromthe burden of more time-consuming, but often simple, synthesis tasks. 1 , 2 FPGA and programmable SoC manufacturers offer their own tools to ease theimplementation of hardware–software systems on them. Examples include  Platform Studio 3 and  FastChip 3 from Xilinx. Although such tools simplify the design process,the designer still needs to manually design individual hardware and software partsand assemble them together using the tool facilities. This makes the design processvery time-consuming and error-prone, and hence, very hard and expensive to makechanges to the partitioning later in the design process.Software-based approaches to hardware design have recently received moreattention.  DK Suite  4 from Celoxica enables the designer to implement hardwarefrom an extended-C source code. Similarly,  Catapult  5 from Mentor accepts C/C++source code. However, none of these tools extend to synthesize a hardware–softwaresystem. Moreover, they do not support object-oriented polymorphism.Other tools, such as  VCC  6 and  SPW  6 from Cadence and  CoCentric System Studio 7 from Synopsys, exist that accept finite-state machine and/or graphicaldesign entry and produce hardware–software systems. System design using suchtools is not generally as easy as programming in C/C++, and hence, such tools arenot likely to have the effect that we wish to see in the popularity of hardware andhardware–software designs among beginners.Focusing on this issue, in this paper we introduce an object-oriented platform-based design process using our ODYSSEY 8 design methodology that advocatesdesigning an “application-specific instruction-set processor” (ASIP) tailored to the  February 6, 2009 10:23 WSPC/123-JCSC 00481 A Framework for Object-Oriented Embedded System Development   975 application-domain being supported; this ASIP can then be programmed to addmissing functionalities and/or to correct malfunctioning parts. The approach isbased on the reuse of hardware and software components and on the configurationof FPGA-based architectural platforms. Our approach aims to ensure a smoothtransition from object-oriented models specified in C++ to the target embeddedsystem. The transition from higher to lower abstraction levels is facilitated by areal-time J# GUI. 9 The remainder of this paper is organized as follows. In Sec. 2, we mention amotivational example and related works. Section 3 reviews the ODYSSEY designmethodology. In Sec. 4, we describe our synthesis flow and the toolset. The struc-ture of system hardware is described in Sec. 5. Section 6 contains case studiesimplemented by our approach. Finally, we conclude in Sec. 7. 2. Motivational Examples and Related Works2.1.  Examples to motivate the methodology and the tool  Suppose we want to implement a JPEG decoder as a hardware–softwareco-designedimplementation. The first step is to describe our desired system with a high-levellanguage such as C/C++, and debug and verify the system functionality. The sec-ond step is the partitioning of methods into hardware and software, and designing aprotocol to connect these parts. In the next step, software designers design softwareparts, and hardware designers design hardware modules. So far, everything soundsgood. The last step is integration and debugging. In this stage, problem begins toappear: how is overall system verified and debugged? Integration of such systemseems to be one of the main challenges. Lack of a well-defined design flow is anotherproblem in designing HW/SW systems. So, if a methodology and tool can gener-ate a HW/SW system from its high-level description and provide debugging andverifying facilities, integration will no longer be a problem. The ODYSSEY doesthis work. The ODYSSEY is a methodology and a tool that provides a frameworkto design, debug, and verify such systems. Moreover, reuse is another importantfeature supported by ODYSSEY. For example, to design a Motion-JPEG decoderfrom scratch, all methods should be developed and debugged, but if a JPEG libraryexists, and it is possible to use this library, the design time intensively decreases.Our tool spans from object-oriented model of application to low HDL model. Inthis paper, we present our methodology and framework for the development of embedded systems based on OO-ASIPs. 2.2.  Related work  A large body of research is available that can be related to this research in onedirection or another. Table 1 lists a number of such works. Vulcan, 11 Cosyma, 12 SpecSyn, 13 Lycos, 14 and Polis 15 have conducted research on hardware–softwarepartitioning. CoWare 16 and Chinook 17 have worked on hardware–software interfac-ing. Cosyn 18 and SOS 19 have focused on hardware–software co-synthesis. Cosmos 20  February 6, 2009 10:23 WSPC/123-JCSC 00481 976  N. Mohammadzadeh et al. Table 1. A number of related works in the area of hardware–softwareco-design and system-level design.Project University Main focusChinook U Washington InterfacingCobra U Tubingen PrototypingCosmos TIMA RefinementCosyma TU Braunschweig PartitioningCosyn Princeton CosynthesisCoware IMEC InterfacingJavatime UC Berkeley RefinementLycos TU Denmark PartitioningPolis UC Berkeley Partitioning, VerificationPtolemy UCc Berkeley Modeling, SimulationSOS U Southern California CosynthesisSpecSyn UC Irvine Specification, PartitioningVulcan Stanford Partitioning and Javatime 21 proposed sets of refinements to gradually implement a hardware–software system from a given specification. Cobra 22 concentrates on prototypingand Ptolemy 23 focuses on modeling and simulation of heterogeneous systems. AsTable 1 clearly shows, there are several issues and concerns in system-level designthat make it impractical and unreasonable, to consider all of them at the sametime. This has made all researchers in the field to focus merely on one, or a few, of such issues, and we are not an exception.Our ESL design methodology is developed on two points:  object-orientation in modeling   and  ASIP in implementation  . These same choices of starting and endingpoints in the design of hardware–software embedded systems comprise the maindifference between our methodology and all other related works; they either do notstart from an OO application or do not implement it as an ASIP. This researchfocuses on the synthesis of an ASIP (its hardware, firmware, and their interface)and on generating the software to run on that ASIP such that the ASIP that isdeveloped for a given set of applications can equally well serve future applicationsthat reside in the same domain. Specifically, regarding partitioning (i.e., the choiceof parts to implement in hardware when the ASIP is first synthesized), ODYSSEYtoolset enables the designer to automatically realize any desired partitioning choice.Four major works exist that directly relate to our methodology: the OASEproject, 24 the ODETTE project, 25 the Silicon Infusion’s Enodia  26 architecture,and work done by Cheng and Wu. 27 A summary of their main features is given inTable 2 to facilitate easier comparison. ODETTE and OASE synthesize ASIC fromthe OO models and consequently do not provide support for application extensionsin future. This contradicts a major feature of OO methodology, i.e., extensibilityand reusability. Enodia (R) has many things in common with our approach, butfollows a bottom-up design flow rather than our top-down flow for applicationdevelopment. In Ref. 27, Cheng and Wu design and implement software objects in
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