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A Fully CMOS Low-Cost Chaotic Neural Network

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Abstract
— A chaotic IC is proposed and fabricated using a0.35
µ
m CMOS technology. The circuit iterates an N-shapedtransfer function that can be modified using two externalvoltages, and is implemented using a three neurons network.The main advantages of the proposed circuit are based on itssimplicity, small area (47 x 57
µ
m
2
), and its MOS-onlyimplementation requiring no more than 15 MOS transistors.Measurements show the suitability of the proposed system toreproduce a chaotic signal and to be used as a randomnumber generator.
I.
INTRODUCTIONhaos refers to the impossibility of making accuratelong-term predictions about the behavior of non-linear systems. During last decades there has been a high interestin the design and analysis of chaotic systems given their parallelism with nature behavior. Other fields of applicationinclude secure communications [1], robot control [2], or implementation of noise sources [3], frequently employed inspeech processing applications or to test the dynamic behavior of electronic systems. Chaotic circuits are also usedas random number generators for applications in the securitydomain of networks and wireless communications [4].“Truly” random number generators may also be used for both analog and digital IC testing [5]. In particular, neuralnetworks exhibiting a chaotic behavior can be applied tooptimization problems [6].Many chaotic oscillator designs were introduced during lasttwo decades. One of the most known chaotic circuits is theChua’s circuit [7,8] containing four linear elements (twocapacitors, one resistor and one inductor) and one nonlinear resistor called Chua’s diode constructed using operationalamplifiers (that may lead to frequency limitation). Anintegrated implementation of Chua’s circuit was presented in[9] fabricated using a 2
µ
m CMOS technology, andoccupying a silicon area of 2.5 x 2.8 mm
2
. This appreciablearea was mainly due to the operational amplifiers. Other researchers [10-12] present different chaotic oscillators usinginductances, resistors and nonlinear elements (similarly toChua’s circuit) that required the use of several operationalamplifiers in their final design.
This work was supported in part by the Spanish Ministry of Science andTechnology, in part by the Regional European Development Funds(FEDER) under EU Project TEC2005-05712/MIC.Authors are with the Physics Departament at the Universitat de les IllesBalears, Palma de Mallorca, Balears, 07122, Spain ( phone +34 971 171373, fax: +34 971 173 426; e-mail: j.rossello@ uib.es).
Fig. 1. Basic neuron scheme. Inputs are added and evaluatedthrough a non-linear function.
clkclk
OUT
V
oa
V
ia
1 234
Fig. 2. General scheme of the chaotic systemTo overcome these area problems a simpler design has beenrecently introduced using a low number of MOS transistors[13]. The circuit implements the double-scroll chaoticequation and its effectiveness is accurately demonstratedthrough PSPICE simulations [13].In this work we present a low-cost fully CMOS chaotic IC.As done in [13], a low area of integration is achieved due tothe use of a relatively low number of transistors. The chaotic behavior is reproduced implementing a N-shaped map usingthree coupled neurons designed with a simple CMOSscheme. The circuit was implemented on a 0.35
µ
mtechnology and integrated in 0.0027 mm
2
of silicon area.The rest of this paper is organized as follows: in section IIwe show the basic principles of the proposed chaotic system,in section III we present the circuit design. Section IV showsthe experimental results and finally, in section V we presentthe conclusions.
II.
C
HAOTIC NEURAL NETWORK
Our design is based in obtaining a chaotic signal from asmall neural network. Neurons are non-linear elements thatimplement a sigmoid-like function (
f
) to the result of addingall its inputs
I
i
(see Fig. 1). Therefore, the neuron response(
y
) can be expressed as:
y
=
f I
i
∑
( )
(1)
A Fully CMOS Low-Cost Chaotic Neural Network
José L. Rosselló, Sebastià Bota, Vicens Canals, Iván de Paul and Jaume Segura
C
Fig.3. Simple CMOS implementation of a 2-inputneuron.
CLKCLKCLKCLK
V
c2
V
c1
V
od
V
oa
V
ia
Fig. 4. Circuit implementation of the chaotic neuralnetwork. Two outputs, an analog and a digital signal (
V
oa
and
V
od
) are obtained.We design a small network composed by three neurons toimplement a N-shaped transfer function
N(x)
as it has beenshown that, under specific conditions, iterations on a N-shaped map may reproduce a chaotic behavior (see [14]). Thestate of the system
x
n
is updated at each iteration through an N-shaped transfer function
N(x
n
)
so that:
x
n
+
1
=
N x
n
( )
(2)The function
N(x)
may be reproduced with three coupledneurons (Fig.2), each one implemented with a CMOScircuitry. A simple two input neuron circuit is shown inFig. 3 (for an n-inputs neuron the scheme is similar). Insubmicron technologies the conductance of parallel-connected MOS transistors operating in the saturation regionis proportional to the sum of their gate voltages. A pMOS pull-up transistor connects the output and the supply voltage(
V
DD
), thus providing a high voltage at the output when bothnMOS devices are in CUTOFF. The sigmoid-like transfer function at the output is obtained due to the non-linear characteristics of nMOS devices that have three conductancestates (CUTOFF, LINEAR and SATURATION, see Fig. 3).A change in the pull-up conductance modifies the transfer function shape (through the transistor gate voltage or devicesize).The proposed circuit for an n-inputs neuron does not providean exact sigmoidal function between the inputs sum and theoutput, but the transfer curve obtained is enough toreproduce the N-shaped transfer function of the neuralnetwork of Fig. 2 (and therefore to reproduce the chaoticsignal).Fig. 5. Photograph of the fabricated prototype
III.
C
IRCUIT IMPLEMENTATION
The circuit implementation of the neural network is shownin Fig. 4. Two output signals, one analog and the other digital (
V
oa
and
V
od
) are provided. Two transmission gatescontrolled by an external clock are serially connected to theneural network. When the clock is low, the voltage
V
oa
isevaluated through
N(x),
while when the clock is high theevaluation
N(V
oa
)
replaces the previous value of
V
oa
. Theresult is the iteration described in (2) at each clock cycle.The digital output (
V
od
) is obtained from
V
oa
using a chain of three inverters being a signal that chaotically switches between logic levels H and L.The inverters threshold voltage is adjusted at the mid-levelof
V
oa
voltage variation to obtain the same numbers of zerosand ones in
V
od
. For the circuit fabricated, this thresholdvoltage was settled at 1.59V.We included two control signals
V
c1
and
V
c2
to modify the pull-up conductance of two neurons in the network (see Fig.4) to have the possibility of changing the transfer functionshape.The proposed circuit was fabricated using a 0.35
µ
m CMOS process. The nominal supply voltage is 3.3V while the totalarea of the circuit is 0,0027 mm
2
(Fig.5).
IV.
E
XPERIMENTAL RESULTS
The transfer function
N(x)
is controlled through signals
V
c1
and
V
c2
. Parameter
V
c1
controls the transfer function shape,while
V
c2
modifies its offset. Figures 6 to 9 show varioustransfer functions measured for different combinations of thetwo controlling voltages. We provide also the identityfunction
y(x)=x
since the output signal is chaotic only whenthe intersection between such a function and
N(x)
occurswhen
N(x)
is decreasing [14]. Figures 6 and 7 show theeffect of varying
V
c1
, while
V
c2
is maintained constant at0.74V. A N-shaped transfer function is obtained when
V
c1
=1.1V
(Fig.6), while for the higher value of
V
c1
a single peak-like curve is obtained (Fig. 7).
V
c2
changes the offset of
N(x)
as shown in Figures 8 and 9when increasing this voltage. As
V
c2
increases theconductance of the third neuron pull-up transistor is lowered,thus decreasing the output voltage
V
oa
. From all thesetransfer functions (Figs 6-9), only the one shown in Fig 6leads to the expected chaotic behavior while the otherscorrespond to a fixed point.
Fig. 6. Transfer function for
V
c1
=1.1V
and
V
c2
=0.74V
Fig. 7. Transfer function for
V
c1
=1.45V
and
V
c2
=0.74V.
Fig. 8. Transfer function for
V
c1
=1.1V
and
V
c2
=1.0V
.Figures 10-12 show the dynamic behavior of the circuitwhen the clock signal oscillates at 1MHz. In Fig. 10 weshow both the digital and analog outputs. The controllingvoltages are set to
V
c1
=1.1V
and
V
c2
=0.68V
leading to achaotic behavior. A similar behavior is obtained with themeasurements taken when
V
c2
is settled to
0.86V
(Fig. 11)
.
Both conditions have a similar N-shaped transfer function asthe one shown in Fig.6.When
V
c2
is greater than 1.0V (Figs. 8 and 9), the transfer function intersection with the identity function changes andthe output behavior becomes a fixed point. This is shown inFig. 12, where a
V
c2
value of 1.0V is selected (the transfer function for these conditions is shown in Fig.8).Fig. 9. Transfer function for
V
c1
=1.1V
and
V
c2
=1.17V
.Fig. 10. Dynamic characteristics for
Vc1=1.1V
and
Vc2=0.68V
We computed the Lyapunov exponents of the system whenvarying
V
c2
while maintaining
V
c1
at
1.1V
. Lyapunovexponents constitute a useful metric for the estimation of thesystem sensitivity to initial conditions. The level of chaos isdirectly related to the Lyapunov exponents values since positive (negative) exponents are related to chaotic (periodic) behavior. Two trajectories with nearby initial conditionsdiverge, on average, at an exponential rate characterized bythe Lyapunov exponent. Therefore, the separation betweentwo trajectories
δ
x
presents an evolution in time given by:
δ
x
k
=
δ
x
0
e
λ
k
(3)where
δ
x
k
is the separation between the trajectories in thek-th iteration, and
δ
x
0
is the initial separation.We computed the Lyapunov exponents using thetechnique described in [15] for different values of
V
c2
(seeFig. 13). It is shown that
λ
is positive when
V
c2
<0.9V
, being in agreement with the change of the crossing point between the identity and the transfer functions observed inFigs. 6,8 and 9. Fig. 14 shows a plot of
V
oa
vs.
V
c2
.
V
c1
isfixed to
1.1V
while
V
c2
is varied from 0 to 3.3V (the voltagescale in the oscilloscope is set to 0.5V per division). It isshown that when
V
c2
is higher than 1.0V the signal becomesa fixed value while for lower values we obtain an oscillatory behavior.
Vc2=0,86V
0,000,501,001,502,002,503,00-50,00 0,00 50,00 100,00
Time (us)
V o a
Fig. 11. Dynamic characteristics for
V
c1
=1.1V
and
V
c2
=0.86V
Vc2=1,0V
0,000,501,001,502,002,503,000,00 20,00 40,00 60,00 80,00 100,00 120,00
Time (us)
V o a ( V )
Fig. 12. Dynamic characteristics for
V
c1
=1.1V
and
V
c2
=1,0V
-0,50-0,40-0,30-0,20-0,100,000,100,200,00 0,50 1,00 1,50 2,00
Vc2 (V)
L y a p u n o v e x p o n e n t
Fig. 13. Lyapunov exponent value as a function of
V
c2
when
V
c1
=1.1V
Finally we computed the autocorrelation of the digitaloutput. The autocorrelation function provides informationabout the similarity of a digital signal
a
i
to itself evaluatedat time
i+k
(
a
i+k
). We define the autocorrelation of a digitalsignal as follows:
C k
( )
=
a
i
⊗
a
i
+
k i
=
1
N
−
k
∑
−
a
i
⊕
a
i
+
k i
=
1
N
−
k
∑
(4)Fig. 14.
V
oa
vs
V
c2
plot when
V
c1
=1.1V
.Fig. 15. Autocorrelation function of
V
od
(5)Where operators
⊗
and
⊕
are the XNOR and XOR logicfunctions respectively. A periodic signal with period
K
has acorrelation function
C(K)=1
while a random signal with a50% of probability of being HIGH or LOW has a correlationfunction
C(k)=0
∀
k>0.
In Fig. 15 we show a comparison of the correlation functions of the digital output
V
od
and theoutput of a 4-bit LFSR. It is shown that the LFSR has alow value of the correlation function except for those casesin which
k
is a multiple of the LFSR period (
C(n
•
15)=1
).The proposed circuit (with a considerable lower number of transistors compared to the LFSR) provides similar valuesfor
C(k),
but without the period of repetition observed in theLFSR.
V.
C
ONCLUSIONS
A very simple fully-CMOS neural network circuitexhibiting a chaotic behavior has been presented andvalidated experimentally on a 0.35
µ
m technology. The mainadvantage of the proposed circuit is its small area and itsimplementation using MOS transistors only. The chaoticnature of the circuit is demonstrated experimentally throughthe computation of the Lyapunov exponents and themeasured time series. The circuit also provides a digitalchaotic signal that can be used as a random number generator.
ACKNOWLEDMENTThis work was supported in part by the Spanish Ministryof Science and Technology, in part by the RegionalEuropean Development Funds (FEDER) under EU ProjectTEC2005-05712/MIC.R
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