A Fully-differential Operational Amplifier Using a New Chopping Technique and Low-Voltage Input Devices

A fully differential operational amplifier design with offset cancellation
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  A fully-differential Operational Amplifier using anew Chopping Technique and Low-Voltage InputDevices Timo Mai ∗ , Konstantin Schmid † , J¨urgen R¨ober † , Amelie Hagelauer ∗  and Robert Weigel ∗∗ Lehrstuhl f¨ur Technische Elektronik, Cauerstr. 9, 91058 Erlangen,Friedrich-Alexander University, Germany, Email: † eesy-ic GmbH, Frauenweiherstraße 15, 91058 Erlangen, Germany  Abstract —A fully differential CMOS operational amplifier ispresented. It uses a new chopping technique that works withoutthe use of switching transistors in the high gain path, resultingin high noise performance and low offset. It is designed in alow-cost 180nm process with a 5V supply voltage. In criticalplaces, such as the differential pair, 1.8V-devices are used, asthey provide much better matching and noise performance, andat the same time have lower parasitics. They are protected frombreakdown conditions by several circuit techniques. Some of them are described below. The operational amplifier is used in adifferential programmable gain amplifier for processing signalsof up to 50kHz bandwith with a SINAD  >  100dB, making itsuitable as a preamplifier for 18-Bit ADCs.  Index Terms —chopping, operational amplifier, gain boosting,1/f-noise, offset, programmable gain amplifier. I. I NTRODUCTION Every precision analog-to-digital converter has two differ-ential input pins, because differential signals are more robustagainst supply voltage noise and have a higher signal swingthan single-ended ones. Many applications use single-endedsignal processing for simplicity, or because the used sensorhas only a single-ended output. In this case, a single-ended-to-differential conversion should be done to drive an ADCwith differential input. This can be achieved with a typicaldifferential amplifier, as seen in Fig.1, where the negativeinput is tied to ground. To achieve a reasonable performance, − +  − + R 2 V  op V  inn R 1 R 2 V  on V  inp R 1 V  out,cm Fig. 1. Typical differential amplifier the inherent imperfections of the opamp, especially offset andnoise, must be supressed, e.g. by chopping. Usually this isimplemented with CMOS switches [6], [2]. In this work, analternative approach is presented, that works without the useof additional transistors in the high gain path.The paper is organized as follows: in the second sectionthe overall structure of the Opamp and the chopping schemeare explained. The third section addresses the input stage andthe circuit techniques, which protect the low-voltage inputtransistors. In the fourth section the high gain folded cascodestage is shown, which utilizes the new chopping technique. Insection V some simulation results are shown, discussed andcompared to similar works. Finally, a conclusion is drawn.II. O PAMP STRUCTURE AND CHOPPING SCHEME The Opamp’s structure is shown in Fig. 2. The two inputvoltages  V  in 1  and  V  in 2  pass a clocked analog multiplexer andthus are mixed to the chopping frequency. The result is routedto the input gm stage, which transforms the input voltagedifference into a current difference. The two currents formthe input signal for the two high gain stages which convertthem back into the voltage domain. The output of each gainstage is alternately connected to one of the output stages. Thusthe signal is mixed down, and the  1 /f  -noise is mixed up tothe chopping frequency.There are two typical ways to implement this, they areshown in Fig. 3. In the voltage mode realization, the gateof the output device is connected over a switch to one of the high-impedance nodes. The switches can be very small,as they don’t need to carry much current. On the downside,the voltages on the two high-impedance nodes are typicallydifferent, so after switching there will occur large spikes fromthe settling of the two nodes. In the current mode realization,the currents from the two current sources are alternatelyconnected to the two cascodes. The two operating pointsdiffer significantly less from each other than in the voltagemode realization. Also, the charge injection spikes occur ata low impedance node and hence should settle faster. Themain drawback is the additional transistor in the signal path,increasing parasitics and routing effort and decreasing voltageheadroom due to its parasitic on-resistance. In this paper, anew current mode realization is shown, that does not needadditional transistors in the signal path. It is described insection IV. 74 978-1-5386-1911- 7/17/$31.00 ©2017 IEEE  V  in 1  V  in 2 inputgmstage out 1 out 2 out 3 out 4 highgainstage 1 out 1 out 2 out 3 out 4 highgainstage 2  V  out 2 ClassABstage 1 V  out 1 ClassABstage 2 Fig. 2. Block diagramm of the Opamp. Each high gain stage controls Class-AB stage 1 and 2 alternatelyFig. 3. The two typical ways to realize chopping: current mode (left) andvoltage mode chopping (right). The cascodes in the current mode approachare not absolutely necessary [4],[5],[7]. V  in 1 V  in 2 V  in 2 V  in 1 M  in 1  M  in 2 I  b I  s 1 R b R ds I  s 1  +  I  s 212 I  b 12 I  b I  s 2 M  b 1  M  b 2 V  cs V  f   V  fp to gain stage  2 to gain stage  1 Fig. 4. Schematic of the input stage with regulation of the drain-source voltageof the differential pair. The folding point  V  fp  follows the input voltage. III. I NPUT  S TAGE WITH FOLDED CASCODE Fig. 4 shows the schematic of the input stage. The short-channel low-voltage devices  M  in 1  and  M  in 2  form the differen-tial pair. At first it is explained why they should be low-voltagedevices.In simplified terms, an opamp’s overall noise contribution isroughly inversely proportional to the transconductance of theinput pair [8],[1]. Thus, a large transconductance is needed.To obtain this at a reasonable power consumption, the  W L  -ratiomust be large.On the other hand, huge input devices have a huge inputcapacitance. In Fig. 1, this parasitic input capacitance occursat the operational amplifier’s input, forming a parasitic pole,or low-pass filter, in the feedback loop with  R 2 . This parasiticpole must be located well beyond the closed-loop bandwidth,otherwise it will noticeably decrease the overall phase margin.This builds a constraint for the product  R 2 · C  g,in .As lowering the value of   R 2  considerably increases powerconsumption, it is necessary to push the input capacitancebelow a certain level while keeping the  W L  -ratio above a certainlevel. This way, a minimum of distortion and maximum noiseperformance can be achieved for a given current consumption.Typically, this problem is addressed by using capacitors inparallel to  R 2  [9]. Then the circuit acts like an integrator,or low-pass filter, for higher frequencies. This has a positiveeffect on stability, because a low-pass filter has a slow stepresponse, and the parasitic pole simply does not occur at thoselower frequencies. On the downside, the slower overall oper-ation of the circuit causes higher distortions when processingfast signals.Next, the operation of the input stage is explained.  V  cs  isroughly one threshold voltage above the input common modelevel. The current  I  s 1  flows through the resistor  R ds , creating aconstant voltage drop and  V  f   is following  V  cs . The transistors M  b 1  and  M  b 2  have the same current densities and thus thesame gate-source voltage. Therefore,  V  fp  follows the inputvoltage keeping the drain-source voltage of the input devicesconstant at V  ds  =  R ds I  s 1 − V  gs,b 1  +  V  gs,b 2  ≈ R ds I  s 1 .  (1) V  fp  will be at the lowest possible level for the minimum inputvoltage (0V). To ensure proper functionality, it still must behigh enough to keep the current sources  12 I  b  in saturation. V  gs,Min  mainly depends on  V  th,Min , which is increased byutilizing the body effect, keeping the bulk-source voltageconstant at  R b I  s 1 . 75  The presented input stage is capable of protecting high-performance low-voltage devices, as every voltage at theirpins is regulated relatively to the input voltage. Every processwith devices for different supply voltages can benefit from thisapproach and optimize the ratio transconductance/bandwidthto power consumtion.IV.  HIGH GAIN STAGE The structure of the high gain stage can be seen in Fig. 5.It works as follows. The current signal from the input stagecontrols the current source  M   p 3 . The output pins  out 1  and out 3  are connected to one of the output stages, the pins  out 2 and  out 4  to the other one. The second gain stage is connectedthe other way around,  out 2  and  out 4  are connected to the firstoutput stage and  out 1  and  out 3  to the second one. Consideringthe chopping control signals  φ  p 1  and  φ n 1  at  V  dd , and  φ  p 2  and φ n 2  at ground, the amplifier  A 1  regulates the cascode  M   p 4 ,while  M   p 6  is shut off. At the same time the amplifier  A 2 regulates the cascode  M  n 1 , while  M  n 2  is shut off. Thus, thefirst gain stage drives the first output stage through  out 1  and out 3 , and the second gain stage drives the second output stagethrough  out 1  and  out 3 . In the other chopping state, the inputswitches in Fig. 4 are toggled, and the cascodes  M   p 6  and  M  n 2 are regulated by  A 1  /  A 2 . Then the first gain stage drives thesecond output stage, and the second gain stage drives the firstoutput stage.In summary, the output of the current sources  M   p 3  and I  b 2  gets alternately routed to one of the two output stagesusing two gain boosted cascodes each. One of them is alwaysswitched off. That way, no additional switching transistor isnecessary.V. S IMULATION  R ESULTS In this section, some simulation results are presented anddiscussed. The opamp is connected as shown in Fig. 1, therebythe differential gain is set to unity, which is the most criticalcase for stability. The amplifier’s input-referred offset voltageis artificially set to 10mV, the chopping frequency is set to500kHz.The first simulation result can be seen in Fig. 6. A constantinput signal of   ∆ V  in  = 1 V is applied. In the ideal case, thisshould also be seen at the output, as the differential gain isset to one. The actual output signal  ∆ V  out  alternates between0.98V and 1.02V. At first this might seem suspicious, as theoffset voltage is only 10mV. Assume the inputs in Fig. 1are both at 0V. Caused by the opamp, which has an offsetof 10mV, it forces the voltage difference at its inputs to be10mV. If   R 1  and  R 2  have the same value, the output voltagedifference must be 20mV. The output signal is filtered bya first-order low-pass filter with 100kHz cutoff frequency( ∆ V  out,lpf  ).The voltages in the upper plot refer to Fig. 5. It showsthe transient behavior of the gain booster’s output voltage andthose at the gates of the cascodes  M   p 4  and  M   p 6 . It shows thegate voltages being alternately switched between  V  dd  and  V  gb .The spikes in  V  gb , that occur at every switching operation, are − + − +      f   r   o   m    i   n   p   u    t   s    t   a   g   e V  b 1 V  b 2 out 1  out 2 out 3  out 4 V  dd φ  p 1 φ  p 2 φ  p 2 φ  p 1 φ n 2 φ n 1 φ n 2 φ n 1  common − modefeedbackV  4 V  3 V  1 V  2 V  gb A 1 A 2 V  reg 1 V  reg 2 I  b 2 M   p 1 M   p 2 M   p 3 M   p 4 M   p 5 M   p 6 M   p 7 M   p 8 M   p 9 M  n 1 M  n 2 M  n 3 M  n 4 M  n 5 M  n 6 Fig. 5. Schematic of the high gain stage. Two instances of this circuit areconnected to the input stage. caused by the cascodes gate capacitance, which needs to becharged from  V  dd  to  V  gb .The second simulation result is shown in Fig. 7. It showstwo simulations of the output noise spectral density, withand without chopping. The 1/f-noise, and thus the offset, ismodulated to the chopping frequency  f  chop . On the other hand,the white noise is modulated to DC and the frequency rangeof interest. A very small amount of 1/f-noise is generated inthe output stages and added to the white noise, because theoutput stages are not chopped. Note that a significant part of the output noise is generated by the feedback resistors.The third simulation result is shown in Fig. 8. It shows thefrequency response of the Opamp and the gain plots of thetwo gain boost amplifiers  A 1  and  A 2  (Fig. 5). It can be seenthat, for the nominal case, the DC gain of the Opamp exeeds140dB, while the phase margin is 86 ◦ at 72MHz. Also, theGBW of the gain boost amplifiers is higher than the Opamp’s,which is essential for a good exponential settling, especiallyin unity-gain feedback. 76  94 94 . 5 95 95 . 5 96 96 . 5 9744 . 55  V  1 V  2 V  gb V 94 94 . 5 95 95 . 5 96 96 . 5 970 . 9811 . 02 time in  µ s ∆ V  in ∆ V  out ∆ V  out,lpf  Fig. 6. Transient response. The upper plot shows the signals in the high gainstage (Fig. 5), the lower plot shows overall behavior of the circuit. 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 − 8 10 − 7 10 − 6 frequency in Hz     n    o     i    s    e    p    o    w    e    r     d    e    n    s     i     t    y     i    n     V  √       H    z   without choppingwith chopping f  chop  = 500 kHz Fig. 7. Simulated output noise with and without chopping 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 050100150 frequency in Hz      l    o    o    p    g    a     i    n     i    n     d     B     /    p     h    a    s    e     i    n       ◦ 72MHz / 86 ◦ Fig. 8. Simulated frequency response of the Opamp (blue, dashed) and gainplot of the gain boost amplifiers  A 1  and  A 2  (Fig. 5)TABLE IT HE OPAMP ’ S SIMULATED WORST - CASE PARAMETER IN COMPARISON TOSIMILAR WORKS parameter this work [2] [3] [10] @5 Vt.-range /   ◦ C -40 - 125 -40 - 125 -40 - 125 -40 - 85 V  dd  / V 5  ±  10% 2.1 - 5.5 1.8 - 5.5 4.5-12 I  supply  / mA 7 1.4 0.017 17 V  in  / V 0... V  dd -1 0- V  dd  0- V  dd  1.15-3.85 V  cm,out  / V 0.8 ...2.7 s.-ended s.-ended 0.55... V  dd -1.3DC gain / dB 106 136 172 68GBW / MHz 43 4 0.35 135phase margin 60 ◦ 63 ◦ ≈ 60 ◦ -/-noise /  nV √  Hz3.5 5.6 55 4.5 Since any offset will be cancelled by the chopping, theresults of Monte-carlo analysis play a minor part in relation tothe worst-case process corners and operating conditions. TableI shows the simulated operating range, lists the resulting worst-case parameters and compares them to recent works on thisfield.VI. C ONCLUSION A new chopping technique for Operational Amplifiers ispresented. It gets by without the use of additional transistorsin the high gain path. A fully-differential opamp that usesthis approach is shown. The input stage uses low-voltagedevices for higher performance and lower parasitics. Someof the circuit techniques used to protect them, such as thefolded cascode with regulated folding point, are described. Theshown techniques are verified by different simulation results,that prove their functionality.R EFERENCES[1] B. Razavi,  Design of Analog Integrated Circuits , McGraw-Hill, 2001.[2] Y. Kusuda,  A 5.6 nV/  √   Hz Chopper Operational Amplifier Achieving a0.5 µ V Maximum Offset Over Rail-to-Rail Input Range with AdaptiveClock Boosting Technique , in IEEE Journal of Solid-State Circuits, Vol.51, No. 9, SEPTEMBER 2016[3] Rod Burt and Joy Zhang,  A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Insidethe Continous-Time Signal Path , in IEEE Journal of Solid-State Circuits,Vol. 41, No. 12, December 2006[4] R. Wu, K. A. A. Makinwa and Johan H. Huijsing,  A Chopper Current-Feedback Instrumentation Amplifier With a 1 mHz  1 /f   Noise Corner and an AC-Coupled Ripple Reduction Loop , in IEEE Journal of Solid-StateCircuits, Vol. 44, No. 12, December 2009[5] H. W. Klein and W. L. Engl,  Design Techniques for Low Noise CMOS Operational Amplifiers , in Tenth European Solid-State Circuits Confer-ence, 1984[6] Christian C. Enz and Gabor C. Temes,  Circuit Techniques for Reducingthe Effects of Op-Amp Imperfections: Autozeroing, Correlated DoubleSampling, and Chopper Stabilization , in Proceedings of the IEEE, Vol.84, No. 11, November 1996[7] M. Dessouky and A. Kaiser,  Very low-voltage fully differential amplifier  for switched-capacitor applications , in IEEE International Symposium onCircuits and Systems, May 2000[8] Gaurav Kumar Sharma, D. Kumar and A. Kumar,  Design of 3 Stage Low Noise Operational Amplifier  , in 2015 International Conference onCommunication, Control and Intelligent Systems[9]  THS413x Datasheet  , revised August 2015,[10]  THS4552 Datasheet  , revised July 2017, 77
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