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A fully-programmable analog log-domain filter circuit

This paper will describe the design of a general purpose continuous-time IF analog filter that utilizes log-domain integrator circuits. The coefficients of the filter are digitally programmable and externally controlled using a serial input data
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  ABSTRACT This paper will describe the design of a general purposecontinuous-time IF analog filter that utilizes log-domainintegrator circuits. The coefficients of the filter are digi-tally programmable and externally controlled using aserial input data stream. Both the poles and the zeros of the filter are adjustable, allowing arbitrary filter func-tion implementation. The filter has been fabricated in a0.8 micron BiCMOS technology and it is capable of 2.5volt operation. The experimental results are included. 1. Introduction Analog filters are one of the most important andwidely used electronic devices, having numerousapplications in analog and mixed-signal consumerproducts. Unfortunately, the costs associated withproducing such filters are high, and it is not costeffective to produce a filter for a specific applicationwith a limited market. It is therefore our intention hereto introduce an analog filter structure that can be massproduced but customized for a particular application.To accomplished this goal, some form of digitallyprogrammable analog filter is required.Log-domain filters with their unique tunabilityproperties and high bandwidth, are excellentcandidates for these programmable filters. Through theuse of a single multi-purpose log-domain integratorcell, we will illustrate a systematic approach fordesigning arbitrary high-order filter functions.Complete pole/zero/gain adjustment is made via asingle off-chip digital bit stream controlling a series of on-chip DAC circuits.The discussion of this paper starts by giving a brief introduction to the log-domain integrator cell. Next,the systematic implementation of an arbitrary state-space filter using a log-domain cell will be shown insection 3. Supporting circuitry will be outlined insection 4. Finally, section 5 will describe theexperimental results of a 3rd-order filter fabricated in a0.8 micron BiCMOS process. 2. The Log-Domain Integrator Cell The basic building block of our log-domain filtercircuit is the multiple-input log-domain integratorcircuit shown in Fig. 1. Both the non-inverting andinverting integrators of [1] are combined to form auniversal log-domain building block with DC stablebehavior [2]. Through the use of this integrator, high-order circuit designs are possible using familiar filtersynthesis methods [1][2]. In this paper we extend these methods to include the well-known state-spaceformulation. Such an approach was adopted first byFrey in [3], however, the approach given there was ad hoc  and limited to only a second-order filterrealization. In this work a third-order example will beused to illustrate the systematic approach. Extension tohigher-orders should be self-evident.  Figure 1 Schematic and symbol of log-domain integrator. The log-domain cell of Fig. 1 is a universal buildingblock in the sense that this one cell can be used torealize the complete filter. No other building block isrequired. The relationship between the inputs (V inp ,V inm , I inp , I inm ) and its outputs (I out , V out ) is,(1)where V T  is the thermal voltage of transistor and Io isthe bias currentThe log-domain filter consists of three separate stages:the input stage, the integrator and the output stage.Theinput stage is realized by setting the input voltages(V inp and V inm ) to zero and driving a current into eitherthe I inp  or I inm  terminal. We leave the detailsmathematical relationships between input and output of each stage for the reader to derive. I out V in (V inp  or V inm )I in  (I inp  or I inm )I o V cc V cc V cc I out V inm V inp CI o I o I o I inp I inm Log-DomainCell V out+-  I  out C t d d Vout  =  I  o  I  in  p + [ ] eV  in  pV  out– ( ) 2 V  T  ------------------------------------       I  o  I  in m + [ ] eV  in mV  out– ( ) 2 V  T  -------------------------------------      –= A Fully-Programmable Analog Log-Domain Filter Circuit Arman Hematy and Gordon W. Roberts Microelectronics And Computer Systems Laboratory, McGill University3480 University Street, Montreal, Quebec, Canada H3A 2A7{arman,roberts} 1-514-398-6029, Fax: 1-514-398-4470 0-7803-4455-3/98/$10.00 (c) 1998 IEEE  Taking as the state variable vector and letting  I  in  = u , wecan conclude that:(6)Here we see that the A-elements are all controllable by indi-vidual bias currents whereas the b-element is not. This some-what takes away from the generality of the designs that canbe implemented, but the realization is still capable of imple-menting arbitrary transfer functions.To implement the remaining equation in the state-spaceformulation, we need a summing circuit. Consider the righthand column of the circuit shown in Fig. 2Using (1) we can describe the behavior of this circuit as:(7)After simplifying and using the transformation given in (4)we can conclude;(8)or collectively as,(9)Combining the integrator and summing sections results inthe general state-space log-domain circuit shown in Fig. 2.It can be easily shown that this circuit satisfies thefollowing state-space equations:  X  ˆ  I o 2 V T C  ---------------- α =  and   b 12 V T C  ----------------12 V T C  ----------------12 V T C  ----------------=  where  α  I  a 11  I  o ---------–  I  a 12  I  o ---------–  I  a 13  I  o ---------–  I  a 21  I  o ---------–  I  a 22  I  o ---------–  I  a 23  I  o ---------–  I  a 31  I  o ---------–  I  a 32  I  o ---------–  I  a 33  I  o ---------–=  I out  I ine 02 V T  -----------      –  I c 1 e 02 V T  -----------      –1  e –  X  12 V T  -----------       … ++=  I out  I in I c 1–  X  1ˆ  I c 2–  X  2ˆ  I c 3–  X  ˆ=  I out  I  – c 1  I  – c 2  I  – c 3  X  ˆ  dI in +=  where d  1=  Figure 2 Full implementation of an arbitrary state-space transfer function using the log-domain cell  CX 1 X 2 X 3 I a11 I a21 I a31 CI a12 I a22 I a32 CI a13 I a23 I a330 I in I out I in0 I c1 I c2 I c3 I d1000000000000 I b1 Summation Section Log-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCellLog-DomainCell I in0 I b2 Log-DomainCell I in0 I b3 Log-DomainCell Integration SectionA matrixInput Section,b Vectorc Vectord Element +-+-+- X 1 X 2 X 3 X 1 X 2 X 3 X 1 X 2 X 3 X 1 X 2 X 3 3. High-Order State-Space Realization In this section we shall demonstrate how one caninterconnect the log-domain cell of Fig. 1 to realize theconventional state-space equations. We shall use a 3rd-order system to illustrate this procedure. Higher-orderdesigns are a direct extension of the circuits describe here.Consider the left column of the circuit shown in Fig. 2, onecan write the following KCL equation,(2)Substituting the appropriate characteristic equationobtained from section 2, we can then write (2) as: resulting in(3)Defining the nonlinear terms between brackets as(4)then we can rewrite (3) as:(5)In a similar fashion, the remaining rows of the state-spaceequation given can be described by:  I out  I out in ( )  I out  1  I out  2  I out  3+++= C t d dX  1  I ine X  12 V T  -----------        –  I a 11 e X  12 V T  -----------        –1  e –  X  12 V T  -----------       … ++= t d d e X  12 V T  -----------         I in 2 V T C  ----------------  I a 112 V T C  ----------------1  e –  X  12 V T  -----------         I a 212 V T C  ----------------1  e –  X  22 V T  -----------       … +++=  X i ˆ e X i 2 V T  -----------        1–= t d d  X  1ˆ [ ]  I in 2 V T C  ----------------  I a 112 V T C  ----------------–  X  1ˆ [ ]  I a 212 V T C  ----------------–  X  2ˆ [ ]  I a 312 V T C  ----------------–  X  3ˆ [ ] = t d d  X  2ˆ [ ]  I in 2 V T C  ----------------  I a 122 V T C  ----------------–  X  1ˆ [ ]  I a 222 V T C  ----------------–  X  2ˆ [ ]  I a 322 V T C  ----------------–  X  3ˆ [ ] = t d d  X  3ˆ [ ]  I in 2 V T C  ----------------  I a 132 V T C  ----------------–  X  1ˆ [ ]  I a 232 V T C  ----------------–  X  2ˆ [ ]  I a 332 V T C  ----------------–  X  3ˆ [ ] =   0-7803-4455-3/98/$10.00 (c) 1998 IEEE  (10)where  α and c are directly related to the DC bias currentsof the individual log-domain cells. It should be obvious atthis point how one can extend the circuit of Fig. 2 to higherorders. 4. Additional Circuits In order to get the desired programmability, it is necessaryto include on-chip programmable DC current sources. Eachcurrent source consists of a simple eight-bit digital-to-analog converter and an eight-bit shift register as shown inFig. 3. The shift registers of the current sources are daisy-chained together so that a single external bit stream can beused to control the current levels of each current source. Acalibration sequence is performed initially to compensatefor any nonidealities that occur during manufacturing.  Figure 3 Digitally controlled current sources The simple current scaler/divider circuits of Fig. 4 can beused as building blocks to implement the entire eight-bitdigital-to-analog converter. The eight-bit DAC circuitgiven in Fig. 5 consists of two four-bit DACs; one for themost significant bits and the other for the least significantbits. The most significant four-bit DAC has sixteen currentscaler blocks that can each push a current  Io  to the output.The least significant four-bit DAC consists of sixteencurrent dividers. Each current divider pushes a current of   Io/ 16   to the output. Consequently, the circuit of Fig. 5 iscapable of generating 256 distinct current levels rangingfrom 0 to  255 ⋅(  Io/16  ).  Figure 4 Schematic and symbol of Current scaler and divider A simulation of the DAC’s output levels was obtained fromHSPICE and is shown in Fig. 6. The stair-case output isclearly visible in the figure, however, there are largeglitches at the switching instances. Since the DAC is to beused as a DC bias current source, the large gliches due toswitching will not affect the operation of the circuit. t d  X  ˆ  I o 2 V T C  ---------------- α  X  ˆ12 V T C  ----------------  I  in +=  I  out  cT  X  ˆ  d   I  in += Serial-InSerial-Out to theClockResetShift-RegisterEight-bit-DAC 8 next current source Io Vref  Vref VddgndIoutgndIout      V    r    e      f     B      i     t gndIoutBitgndIout      I      i    n     B      i     t Iina) Current Scaler b) Current dividerBitBit Bit  Figure 5 Simple low-power static eight-bit DAC  Figure 6 Sweep of the output current levels of the eight-bit DAC  5. Experimental Results Following the principles laid down in the previous sections,a digitally-tunable third-order state-space log-domain filterwas designed for a 0.8  µ m BiCMOS technology. Recentlythe chip returned from fabrication and a micrograph of itslayout is shown in Fig. 7.  Figure 7 Micrograph of a third-order programmable analog filter fabricated in a 0.8 µ  m BiCMOS technology. Iout      V    r    e      f     B      i     t Iout      V    r    e      f     B      i     t Iout      V    r    e      f     B      i     t Iout      V    r    e      f     B      i     t Iout      V    r    e      f     B      i     t Iout      V    r    e      f     B      i     t Iout      V    r    e      f     B      i     t Iout      V    r    e      f     B      i     t Iout  Vr  e f   B i    t    Iout  Vr  e f   B i    t    Iout  Vr  e f   B i    t    Iout  Vr  e f   B i    t    Iout  Vr  e f   B i    t    Iout  Vr  e f   B i    t    Iout  Vr  e f   B i    t    Iout  Vr  e f   B i    t    Iout      I      i    n     B      i     t Iout      I      i    n     B      i     t Iout      I      i    n     B      i     t Iout      I      i    n     B      i     t Iout      I      i    n     B      i     t Iout      I      i    n     B      i     t Iout      I      i    n     B      i     t Iout      I      i    n     B      i     t Iout I   i   nB i    t    Iout I   i   nB i    t    Iout I   i   nB i    t    Iout I   i   nB i    t    Iout I   i   nB i    t    Iout I   i   nB i    t    Iout I   i   nB i    t    Iout I   i   nB i    t    VddgndVddB0B1B2B3B6B5B7B4Iout Vref  455666777777776X333333301122223X 0250n500n750n1.0uTime (s)0.0u-28.5u-57.0u-85.5u-114.0u-142.5u-171.0u    O  u   t  p  u   t   C  u  r  r  e  n   t   (   A   ) Capacitor Arrays Digitally ProgrammableCurrentSources Log-domain Integrators 0-7803-4455-3/98/$10.00 (c) 1998 IEEE  The gain of the filter can also be controlled through theconfiguration bit-stream and an example of gain adjustmentis shown in Fig. 10.  Figure 10 Gain scaling of the filter Table 1 summarizes the characteristics of the third orderprogrammable log-domain filter. 6. Conclusion The design of a 3rd-order digitally-programmablecontinuous-time log-domain filter in a 0.8 micron BICMOSprocess was described. It was shown that pole-zero andgain tunability is possible for high-speed operation of thefilter. Fine tuning of the response is also possible, but abetter search algorithm is required. Presently, automatedoptimization procedures are being explored. Suchprocedures will allow for more accurate positioning of poles and zeros. Furthermore, it will be possible toconfigure the filter for other transfer functions. Acknowledgments  The authors thank Mourad El-Gamal for sharing his designsand Nazmy Abaskharoun for his assistance with the testsetup and associated programs. References [1] D. Perry and G. W. Roberts, “The Design of Log-Domain Filters BasedOn the Operational Simulation of LC Ladders,” IEEE Trans. on Circuitsand Systems -- II: Analog and Digital Signal Processing, Vol. 43, No.11, pp. 763-774, Nov. 1996.[2] M. El-Gamal and G.W. Roberts, “LC Ladder-Based Synthesis of Log-Domain Bandpass Filters,” IEEE International Symposium on Circuitsand Systems, Hong Kong, pp. 105-108, June 1997.[3] D.Frey, “Log-domain filtering: an approach to current-mode filtering,” inIEE Proc., Vol. 140, No.6, pp.406-416, Dec. 1993.[4] D. A. Johns and A. S. Sedra, “State-Space simulation of LC Ladder Fil-ters,” IEEE Trans. on Circuits and Systems, Vol. 34, pp. 986-988,August 1987. Table 1: Characteristic of the programmable filter Die Size1mm 2 Supply Voltage> 2.5VPower Consumption70 mWMaximum Operating Frequency8 MHzAdjustable Stop-band Attenuation20 to 50 dBTHD (for input modulation level of 50%)1.0%Third-order intercept (input tone @ 200kHz)35 dB    P  o  w  e  r   (   d   B  m   )  Frequency (kHz) The chip occupies an area of 1000  µ m by 1000 µ m. Usingintegrating capacitors of 20 pF and a nominal bias currentof 200 µ A. The chip dissipates approximately 70 mW of power. For a current bias of 200 µ A, the filter circuit iscapable of operating between 2 to 8 MHz.Fig. 8(a) and (b) illustrate the behavior of the filter whenprogrammed for a lowpass response with different cut-off frequencies and stop-band attenuations. The figure showshow the filter's pass-band edge frequency is tuned from 2MHz to 8 MHz. As the frequency is increased, the notchesbecomes less defined, but remain clearly visible.The stop-band attenuation of the filter can also beprogrammed over a wide range. Note that the two mostattenuated cases shown in Fig. 8(b) reveal the presence of asecondary zero. This secondary zero sets a limit to themaximum possible stop-band attenuation; the source of thezero is suspected to be associated with the test setup.  Figure 8 Frequency response of the 3rd order low-pass filter(a)Frequency scaling (b) Stop-band attenuation Figure 9 Fine tuning of the pass-band region Fig. 9 illustrates how the filter can be coarsely tuned so thatit gives elliptic, chebyshev or butterworth responses with apassband attenuation of 0.5 dB. As is evident theButterworth passband behavior is slightly larger thanexpected. This is contributed to the lack of precision in thepresent tuning algorithm. (a) Frequency Scaling(b) Stop-band Attenuation  Frequency (kHz) Frequency (kHz)    P  o  w  e  r   (   d   B  m   )   P  o  w  e  r   (   d   B  m   )  ButterworthChebyshev Elliptic 2000 40006000800010000 Frequency (kHz)    P  o  w  e  r   (   d   B  m   ) -70-60-50-40-30-35 0-7803-4455-3/98/$10.00 (c) 1998 IEEE
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