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A high-speed oscillator-based truly random number source for cryptographic applications on a smartcard IC

A high-speed oscillator-based truly random number source for cryptographic applications on a smartcard IC
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  A High-Speed Oscillator-Based Truly RandomNumber Source for Cryptographic Applicationson a Smart Card IC Marco Bucci, Lucia Germani, Raimondo Luzzi,  Member  ,  IEEE  ,Alessandro Trifiletti, and Mario Varanonuovo,  Member  ,  IEEE  Abstract —The design of a high-speed IC random number source macro-cell, suitable to be integrated in a Smart Card microcontroller,is presented. The oscillator sampling technique is exploited and a jittered oscillator which features an amplified thermal noise sourcehas been designed in order to increase the output throughput and the statistical quality of the generated bit sequences. The oscillatorfeedback loop acts as an offset compensation for the noise amplifier, thus solving one of the major issues in this kind of circuit. Anumerical model for the proposed system has been developed which allows us to carry out an analytical expression for the transitionprobability between successive bits in the output stream. A prototype chip has been fabricated in a standard digital  0 : 18 m  n  -wellCMOS process which features a 10Mbps throughput and fulfills the NIST FIPS and correlation-based tests for randomness. Themacro-cell area, excluding pads, is  0 : 0016 mm 2 ( 184 m  86 m ) and a  2 : 3 mW   power consumption has been measured. Index Terms —Random number generator, noise source, jittered oscillator, Smart Cards.  1 I NTRODUCTION T HE  expanding use of digital communications, electronicfinancial transactions, and digital signature applicationshas raised demanding security issues to fulfill the require-ments for secrecy, integrity, and nonrepudiability of ex-changed information. In this context, cryptographicalgorithms and cryptographic tokens, like Smart Cards,play a fundamental role [1].Both symmetric and asymmetric ciphering algorithmsrequire the availability of a high quality random numbersource for secret key generation [2]; random numbers arealso used for generating challenges in authenticationprotocols, to create padding bytes and blinding values [3].Even if pseudorandom number generators (PRNGs) based on cryptographically secure deterministic algorithms[4] are usually employed for these purposes, a physicalsource of true randomness is needed for algorithm seeding.For this reason, a Smart Card microcontroller alwaysfeatures a truly RNG among its peripheral devices.The main feature of a well-designed RNG is theunpredictability of the produced bit stream: A potentialattacker must not be able to carry out any useful predictionabout the generator’s output even if its design is known.A truly RNG produces a random bit stream from anondeterministic natural source; electronic noise and radio-active decay are two examples of usable processes [5]. Inintegrated implementations, thermal and shot noise areactually the only white stochastic processes which can beexploited. Moreover, these noise sources have predictableand technology-independent distributions, thus allowing usto obtain a statistical model for the RNG.WhendesigninganRNGcoreforSmartCardintegration,awidespectrumofimplementationissueshastobeconsideredand fulfilled. Due to cost reasons and mechanical stressrequirements, the silicon area is a limited resource in SmartCardmicrocontrollers(atypicalchipareaisabout 10 mm 2 fora 32-bit card) and, at the same time, there is the demand tointegrate nonvolatile memory blocks of ever-increasing size.As a consequence, the silicon area for integrating the CPUcoreanditsperipheraldeviceshasto beminimized:Usually, justasmallpercentageofthetotalchipareaisassignedtotheRNG macro-cell. Furthermore, no external components can be used due to packaging constraints and security reasons:Any externally accessible circuit node seriously affects thechip tamper resistance [1].Power consumption is another stringent constraint, espe-ciallyinhand-heldequipmentsuchasmobileterminals[6];if the RNG analogcircuits feature excessivepower dissipation,complex power management policies have to be implemen-ted at the software level in order to meet the requirement forpowerconsumptionduringcardoperation.Arelatedissueisthe chip resistance to power analysis attacks [7]: A currentconsumption waveform highly correlated to the RNG’soutput bit stream can be exploited by an external attacker toextract the generated secret values. IEEE TRANSACTIONS ON COMPUTERS, VOL. 52, NO. 4, APRIL 2003 403 .  M. Bucci and L. Germani are with Gemplus S.A., Rome Crypto DesignCenter, V. Pio Emanuelli 1, I-00143 Rome, Italy.E-mail:, .  R. Luzzi is with Infineon Technologies Austria, Development Center Graz,Babenbergerstrasse 10, A-8020, Graz, Austria.E-mail: .  A. Trifiletti and M. Varanonuovo are with the Electronic EngineeringDepartment, University of Rome “la Sapienza”, V. Eudossiana 18,I-00184, Rome, Italy.E-mail:, Manuscript received 15 May 2002; revised 22 Nov. 2002; accepted 22 Nov.2002.For information on obtaining reprints of this article, please send e-mail, and reference IEEECS Log Number 117860. 0018-9340/03/$17.00    2003 IEEE Published by the IEEE Computer Society  Few noise-based IC RNG designs are reported in theliterature due to the classified nature of most researches inthis field; however, three different techniques for generatingrandom streams are widely exploited: direct amplificationof a noise source [8], [9], jittered oscillator sampling [10],[11], [12], and discrete-time chaotic maps [13], [14].Hardware RNGs can feature a very high throughput, but, even if well-designed, the produced bit streams usuallyshow a certain level of correlation due to bandwidthlimitation, fabrication tolerances, aging and temperaturedrifts, and deterministic disturbances. Substrate and powersupply interference are a major concern since their powerlevels can be higher than the random noise level if properdesign techniques are not employed. To address thisproblem, in [15], a truly RNG which adopts a mixing of the three mentioned RNG methods is presented. Agenerator resistant to deterministic interference is achievedwithout employing any special circuitry even if, due to themixing of different techniques, it is difficult to perform arigorous statistical analysis of the system.A common procedure to remove statistical imperfectionsin the output bit stream from hardware RNGs is to processthe sequence with a carefully designed correcting ordecorrelating algorithm which, from a high speed near-random input stream, generates a lower speed bit streamwith increased statistical quality, “distilling” the entropycontained in the input sequence. In [16], an adaptativedecorrelating algorithm is reported which dynamicallymodifies its compression ratio according to the statisticalproperties of the input sequence and can reveal failures andexternal attacks.This paper presents the design of a high-speed, thermalnoise-based, mixed-signal RNG IC macro-cell, suitable to beintegrated in a Smart Card microcontroller, which features a10Mbpsoutput.TheproposedtrulyRNGexploitsthejitteredoscillator technique, where the sampling oscillator is pro-vided with an amplified noise source in order to achieve ahigh jitter to mean period ratio. In fact, this random numbergeneratorcanbeseenasanamplifiednoisesourcedrivinganA/D converter where only the LSB is used as output.In Section 2, the architecture of the proposed RNG isdescribed, an accurate model for the system is developed,and an analytical expression for the output bit transitionprobability is carried out. Circuit details are reported inSection 3 with special emphasis on the sampling oscillatordesign. Finally, in Section 4, the experimental results on thefabricated prototype are reported which show the random-ness tests performed on the designed generator. 2 RNG D ESIGN The design of truly RNGs using the oscillator methodexploits the random cycle-to-cycle time drift (jitter) in freerunning oscillators to produce a random bit sequence. In thesimplest implementation, a low frequency oscillatorsamples a fast oscillator in a D flip-flop: If the low frequencyoscillator period features a standard deviation much greaterthan the fast oscillator period, the states of the sampledoscillator in two successive sampling times can be assumeduncorrelated (i.e., independent), thus generating a random bit stream.A fully digital implementation which employs CMOSstandard-cell ring oscillators can be used for the describedsystem. The required oscillator jitter level is related to thedesired random stream speed. Experimental results (seeSection 4) have shown a jitter-to-mean period ratio lowerthan  10  4 for CMOS ring oscillators in a  0 : 18 m  digitallibrary, thus limiting the maximum throughput to 100kbps,if a 1GHz fast oscillator is employed.In order to achieve faster bit rates, the proposed trulyRNG, shown in Fig. 1, features a full-custom oscillatorprovided with an amplified noise source, as described inSection 3, which yields a standard deviation of about10 percent of the period length. Such a high jitter level isable to provide a good quality random stream even if a10MHz frequency is adopted for the oscillator meanfrequency.The high speed oscillator has been implemented with a10-stage CMOS ring oscillator that typically oscillates at1 GHz. Furthermore, in order to remove the biasing of theoutput bit sequence due to an unbalanced duty cycle fromthe ring oscillator, a T flip-flop is used as a sampling circuit.This detail ensures an output stream with an unbiasedmean value. However, the effect of an unbalanced sampledoscillator must be taken into account when evaluating thetransition probability between successive bits, as shown inthe following.In Fig. 1, a programmable prescaler is also shown at theoutput of the low frequency oscillator: Scaling factors from1 to 128 are provided in order to experiment different jitterto mean frequency ratios. In a final release for production,this prescaler could be used to lower the output bit rate if adecrease in randomness (e.g., due to process variations,aging and temperature drifts) is detected by the digitalpostprocessor [16].To characterize the noise source statistical behavior, ananalytical expression for the bit transition probability of theraw sequence  BIT  ½ i   before the postprocessor has beencarried out under the following hypotheses: .  A Gaussian probability density is assumed for the T  CLK  RNG  random variable, as shown in Fig. 2. .  The fast oscillator jitter is neglected, according to theprevious considerations. .  An integer frequency ratio is considered: N   ¼  T  CLK  FAST  E T  CLK  RNG f g ;  ð 1 Þ where  E   f g is the expected value operator. It must beobserved that this is a worse-case assumption sincenoninteger frequency ratios produce bit streams 404 IEEE TRANSACTIONS ON COMPUTERS, VOL. 52, NO. 4, APRIL 2003 Fig. 1. RNG architecture.  which look more random when a randomness test isapplied. .  A starting phase shift  t 0  2 ½ 0 ;T  CLK  FAST  Þ  is considered.The transition probability between successive bits isdefined as P  t  ¼  P BIT  ½ i  6¼  BIT  ½ i  1 f g ;  ð 2 Þ where, for an ideal random sequence, it holds that  P  t  ¼  0 : 5 .From Fig. 2, the following expression can be carried out: P  t  ¼ X þ1  j ¼1 Z   ð N  þ  j þ d  Þ T  CLK FAST  þ t 0 ð N  þ  j Þ T  CLK FAST  þ t 0  p T  CLK  RNG ð Þ dT  CLK  RNG ;  ð 3 Þ where,  d   2 ½ d  min ;d  max   is the fast clock duty cycle and  p T  CLK  RNG ð Þ  is the jitter probability density function. Theabove expression can be approximated, limiting the sum to  j  2 ½  j max ; þ  j max  , where  j max T  CLK  RNG    3  T  CLK  RNG f g  and  T  CLK  RNG f g  is the jitter standard deviation.Finally, introducing the complementary error function,for  P  t  it holds that P  t  ¼ X þ  j max  j ¼  j max 12 erfc jT  CLK  FAST   þ t 0  ffiffiffi 2 p    T  CLK  RNG f g " #(  12 erfc j þ d  ð Þ T  CLK  FAST   þ t 0  ffiffiffi 2 p    T  CLK  RNG f g " #) : ð 4 Þ From (4), the main RNG’s parameters have to be chosento fulfill the constraint P  t  ¼  0 : 5 ð 1  " Þ ;  8 t 0  2 ½ 0 ;T  CLK  FAST  Þ ; 8 d   2 ½ d  min ;d  max  ; where  ½ d  min ;d  max   is the assumed range for the fast clockduty cycle and  "  is the desired probability error.If   T  CLK  FAST   ¼  25 ns ,   T  CLK  RNG f g ¼  10 ns , and  d   2 ½ 0 : 4 ; 0 : 6  ,the function  P  t ð d;t 0 Þ  is plotted in Fig. 3 and it results 0 : 37    P  t    0 : 63 . The probability values for faster ringoscillator frequencies are reported in Table 1. It can benoted that, for high  CLK  FAST   frequencies, the effect of   t 0  becomes negligible and the transition probability  P  t approaches the duty cycle  d  . As a consequence, to obtaina good quality random sequence, a fast and balanced CLK  FAST   signal is needed.The low-speed oscillator is based on a triangular waveoscillator [17] where an amplified thermal noise source isadded in the loop before the Schmitt trigger, as depicted inFig. 4. A transconductance amplifier is used to reduce thetriangular signal at the charge pump’s output, thusincreasing the output jitter. In Fig. 5, the amplifier’s noisyoutput signal  V   ð t Þ  is shown: Its period is T  CLK  JIT   ¼  t 1  þ t 2 ;  ð 5 Þ where  t 1  and  t 2  are independent random variables with thesame statistical proprieties, in particular, being V   ð t Þ ¼  V TL  þ st þ v n ð t Þ ;  ð 6 Þ where  v n ð t Þ  is the noise process at the amplifier’s outputand  s  is the triangular wave slope, it follows: t 1  ¼  V   TH   þ  V   TL j j v n ð t Þ s :  ð 7 Þ Finally, from (5) and (7), for the  CLK  RNG  signal, it results E T  CLK  RNG f g ¼  2 N  PRE  s V   TH   þ  V   TL j jð Þ ð 8 Þ BUCCI ET AL.: A HIGH-SPEED OSCILLATOR-BASED TRULY RANDOM NUMBER SOURCE FOR CRYPTOGRAPHIC APPLICATIONS ON A... 405 Fig. 2. Oscillator output signals.Fig. 3. Bit transition probability  P  t . TABLE 1Bit Transition Probability  P  t  versus Fast Clock Period  T  CLK  FAST  Fig. 4. Triangular wave oscillator.   T  CLK  RNG f g ¼  ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 N  PRE  p  s  v n f g ;  ð 9 Þ where the prescaler factor  N  PRE   has also been taken intoaccount, even if the presented design will assume N  PRE   ¼  1 .The triangular wave slope  s  and the white noise rmsvalue   v n f g  can be expressed as a function of the circuitparameters in Fig. 4; in particular, it holds s  ¼  I  SAT  C  1 G 1 R L G  ð 10 Þ  v n f g ¼  ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4 kTB  W  2 R NOISE  G 2 p   :  ð 11 Þ Using the values reported in Table 2, it results  v n f g ¼  35 mV rms;E T  CLK  RNG f g ffi  101 ns; and  T  CLK  RNG f g ffi  7 : 2 ns; thus obtaining a 10Mbps output random stream with atransition probability  P  t  ¼  d  , if a 1GHz fast clock isemployed. 3 C IRCUIT  D ETAILS The complete circuit schematic of the proposed RNG isdepicted in Fig. 6: The triangular wave oscillator has beendesigned using the parameter values reported in Table 2and, to minimize the deterministic interference at the noiseamplifier’s input, two separate power supplies are used forthe linear analog blocks and the switching circuits,respectively. Moreover, a signal to switch off the generatoris provided to reduce the card consumption when random bits are not needed. The power supplies are also auto-matically switched off when the output FIFO is full,exploiting the small start-up time featured by the jitteredoscillator.A two-stage CMOS topology has been used for the noiseop-amp, with a PMOS input stage in order to maximize thecircuit PSRR. The main closed loop op-amp parameters aresummarized in Table 3. Note that the output noise is greaterthan the value carried out from (11) due to the noisecontributions of the amplifier itself. 406 IEEE TRANSACTIONS ON COMPUTERS, VOL. 52, NO. 4, APRIL 2003 Fig. 5. Noisy triangular wave. TABLE 2RNG Circuit Parameters Fig. 6. RNG complete schematic.  A digital postprocessor has been included in thedesigned prototype which features a  16  32  bit FIFO asinterface between the RNG’s asynchronous output and theSmart Card system bus. For testing purposes, the jitteredoscillator’s output  CLK  RNG  is available on pad. The fastring oscillator’s output  CLK  FAST   can also be observed tomeasure the actual oscillating frequency.Finally, in Fig. 7, a back-annotated simulation of thetriangular wave oscillator is shown: The  V   CHG  signal (thinline) is the capacitor voltage at the charge pump’s output,whereas the thick line represents the comparator’s output CLK  JIT  . The clock period is about  107 ns  and a very shortstart-up time is achieved (about  450 ns ). During the start-uptime, the oscillator feedback loop compensates for theamplifier offset, thus solving one of the major issues in thiskind of circuits, compared with other oscillator-based RNGswhere a noise controlled VCO is exploited [11]. 4 E XPERIMENTAL  R ESULTS A prototype of the presented RNG was fabricated in a 0 : 18 m  n -well 1-poly 6-metal CMOS process available fromTSMC. The macro-cell area, excluding pads, is  0 : 016 mm 2 ( 184 m  86 m ).A  3 : 3 V    supply has been used for the analog circuits,whereas the digital part, including the ring oscillator, thesampler, the postprocessor, and some test logics, has beensynthesized on a  1 : 8 V    digital library available from ArtisanCorp. The total macro-cell power consumption is about 2 : 3 mW  .Mean period, jitter, and duty cycle of the triangular waveoscillator have been measured on several chip samples inorder to obtain an estimate of the circuit sensitivity toprocess variations. The measured values are reported inTable 4, whereas, in Fig. 8, an oscilloscope snapshot isdepicted which shows the high jitter level achieved for the CLK  RNG  signal. From Table 4, it follows that the RNG’soutput rate is very close to 10Mbps, the rms jitter value isabout  9 ns , and the circuit is highly insensitive to processvariations. A very good agreement with the back-annotatedsimulation results is achieved, e.g., a 7 percent maximumerror has been observed for the mean period.Temperature stability has been also verified: Meanperiod and jitter variations over the 0-70  C temperaturerange are summarized in Table 5.The fast CMOS ring oscillator measured parameters arereported in Table 6 for different dies. As shown in Fig. 6, thefast oscillator’s output is scaled down for testing purposes:In Table 6, the actual frequency is also shown. The 1 GHztarget frequency has been almost matched and, as expected,its jitter level is negligible with respect to the low frequencyoscillator.Long bit streams have been acquired using a digitaloscilloscope and a PC data acquisition board to control thechip operation. Using the measured bit streams, for the bittransition probability of the raw sequence  BIT  ½ i  , it results BUCCI ET AL.: A HIGH-SPEED OSCILLATOR-BASED TRULY RANDOM NUMBER SOURCE FOR CRYPTOGRAPHIC APPLICATIONS ON A... 407 TABLE 3Op-Amp Characteristics Fig. 7. Back-annotated oscillator simulation. Fig. 8. Jittered oscilator measure ( CLK  JIT  ). TABLE 4Measured Parameters of the Triangular WaveOscillator Output  CLK  RNG
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