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Analytic transient solution of SCFL logic gates

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Analytic transient solution of SCFL logic gates
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  INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl.  2005;  33 :365–378Published online in Wiley InterScience (www.interscience.wiley.com). DOI: 10.1002/cta.326 Analytic transient solution of SCFL logic gates Alberto Maria Bersani 1 , Francesco Centurelli 2 ; ∗ ; † ,Luca Fontana 2 and Alessandro Triletti 2 1 Dipartimento di Metodi e Modelli Matematici per l’Ingegneria ;  Universita di Roma ‘La Sapienza’ ; Rome ;  Italy 2 Dipartimento di Ingegneria Elettronica ;  Universita di Roma ‘La Sapienza’ ;  Rome ;  Italy SUMMARYIn this paper we propose the analytical solution of switching transients for SCFL logic gates. Theanalysis of an SCFL logic gate is carried out without linearization and can be brought back to multipleanalyses of a basic cell, given by a dierential pair with switching input voltages and a variable tailcurrent, to take the eect of series-gating into account. The dierential equation for this cell is a Riccatiequation, if a quadratic current–voltage relationship is used for the transistors, and it can be solved bythe innite power series method, in case of polynomial input signals. An algorithm is proposed toanalyse the full transient of a complex SCFL gate. This provides a closed form expression for transientsignals in terms of circuit and device parameters, that can be used for symbolic analysis or fast time-domain numerical simulation. Some case studies are presented for SCFL gates using OMMIC ED02AHtechnology, and a good agreement between the proposed model and SPICE simulations using complexdevice models is obtained. Copyright  ?  2005 John Wiley & Sons, Ltd. KEY WORDS : SCFL circuits; transient analysis; analytical solution; Riccati equation; symbolic analysis 1. INTRODUCTIONHigh-frequency digital communication systems, e.g. bre-optic communication systems, re-quire high-speed digital circuits to perform essential functions such as decision circuits,time-division multiplexing and demultiplexing, frequency dividers, etc. In these applications,maximum operating speed is often of more concern than power consumption, and emitter-coupled logic families (ECL, CML, MCML) are used to exploit the advantages of the dier-ential topology in terms of speed, symmetry and CMRR [1,2]. Very high speed circuits arecommonly designed in III–V eld-eect transistor technologies (GaAs or InP HEMTs), andSCFL logic is used to implement digital functions [3,4]. ∗ Correspondence to: Francesco Centurelli, Dipartimento di Ingegneria Elettronica, Universita di Roma ‘La Sapienza’,Via Eudossiana 18, I-00184 Roma, Italy. † E-mail: fcentur@ieee.org Received 5 August 2004 Copyright  ?  2005 John Wiley & Sons, Ltd.  Revised 5 May 2005  366  A. M. BERSANI  ET AL . Evaluating the characteristic parameters of logic circuits, such as transition time, propagationdelay, maximum operating frequency, set-up and hold times, and optimizing their performance,can be simply obtained by repeatedly running a circuit simulator. However, using transistor-level circuit simulators with continuous-time modelling of the devices, like SPICE, can bevery expensive in terms of storage and CPU times, resulting impractical in case of largeintegrated circuits. Moreover, the simulator cannot gain an insight into the critical device andcircuit parameters that most aect circuit performance, so analysis using numerical methodsis not useful to the designer, since it is dicult to separate the eect of design parameters.To alleviate this problem, several delay models have been proposed [5–8], since propaga-tion delay is one of the most critical performance parameters in digital VLSI circuits, andmuch eort has been devoted to the extraction of accurate, analytical expressions for timingmodels of basic circuits, which can be incorporated in switch and logic simulators, opti-mizing the design procedure. Clear knowledge of the contribution of each technological andstructural parameter to the delay allows direct denition of optimization rules for performance-driven circuit design. Still more important is the availability of analytical models of switchingtransitions of logic gates, that allow a better estimation of propagation delay, and also tocalculate other performance parameters, that could be of interest for dierent applications(e.g. digital communications). Analytical models can thus be used for automatic optimizationof cell design. An  analytical  , as opposed to a  numerical   response, makes more evident thefunctional relationship between design goals and designable device parameters. For example,signal propagation delay or power dissipation can be shown to have a functional relationshipto transistor dimensions, load capacitance and input signal shape. Analytical expressions of the output waveform are directly obtained from the dierential equations describing the tem- poral evolution of the circuit output, using dierent levels of approximation to nd a trade-o  between accuracy and computational complexity [9–12].In case of CMOS logic circuits, the analytical solution of switching transients has beenobtained without device linearization [13,14], by dening a generalized CMOS circuit primi-tive (generalized inverter) and using the Shichman–Hodges model for MOS devices [15]. Theresulting state equation is a Riccati equation, that can be solved in closed form only under suitable hypotheses for the behaviour of input signals [13].In this paper we extend this analytical approach to the case of SCFL =  MCML logic circuits, providing for the rst time an analytical model without linearization of device equations: inSection 2, basic properties of SCFL gates are reviewed. In Section 3 we obtain the dierentialstate equation for the basic SCFL cell (dierential pair with variable tail current) and discussits solution. In particular, we focus on the power series solution, that provides a symbolicclosed-form solution of the equation with minimal computation cost. In Section 4 we discussthe application of the proposed method to study SCFL gates, and some case studies are presented in Section 5 to assess the accuracy of the proposed method.2. SOURCE-COUPLED FET LOGICSource-coupled FET logic (SCFL) has been proposed as a high-speed logic family for FETdevices with low sensitivity to dispersion of device characteristics [16,17]. Like bipolar emitter-coupled logics (e.g. ECL), SCFL implements combinatorial functions by switching aconstant current between two dierent paths. The basic cell is the buered dierential pair, that Copyright  ?  2005 John Wiley & Sons, Ltd.  Int. J. Circ. Theor. Appl.  2005;  33 :365–378  ANALYTIC TRANSIENT SOLUTION OF SCFL LOGIC GATES  367 Figure 1. Three-input SCFL NAND gate. implements the inverter function; its transistors switch between cuto and saturation, never entering the triode region, allowing very fast transients.The main advantages of SCFL are high speed, high common-mode rejection, availabilityof complementary functions, low sensitivity to threshold voltage variations and to noise, logiclevels independent of fan-in and fan-out. However this requires high static power dissipation,high transistor count, high supply voltage and dierential signalling.Complex logic gates can be implemented by exploiting the series gating technique: a series-gated structure is composed of a series of cascaded stages, and each stage acts as a currentswitch between two branches. This allows reusing the same tail current, thus minimizing power dissipation at the expense of an increased supply voltage. Several paths are thus provided for the tail current by stacking dierential pairs, and current summation on the loads yields twocomplementary outputs. As an example, Figure 1 shows a three-level NAND gate: the tailcurrent ows in the resistor   R L1  only when the three inputs  A ,  B  and  C   are simultaneouslyhigh, yielding a low logic level as output. This gate thereby implements the NAND functionof its three inputs on the output  X  , and its complement on the output  Y  .Similar techniques, known as folded source-coupled logic (FSCL) [18] and MOS cur-rent mode logic (MCML) [19], have been proposed for very high speed digital applicationsin CMOS technology, and the analysis in this paper also applies to these circuitcongurations.3. ANALYTICAL TRANSIENT SOLUTION OF THE BASIC SCFL LOGIC CELLIn this section we obtain the dierential equation for the transient behaviour of the basicSCFL cell, and discuss its solution. To describe the dynamic behaviour of a generic SCFLgate, the fundamental cell we have to consider is a dierential pair with a variable tail current,that allows to take the eect of series gating into account; collector currents are consideredas output variables.Transistors are described by a simplied large-signal equivalent circuit, composed of thegate-source capacitance  C  GS  and the non-linear drain current generator: this allows to represent Copyright  ?  2005 John Wiley & Sons, Ltd.  Int. J. Circ. Theor. Appl.  2005;  33 :365–378  368  A. M. BERSANI  ET AL . Figure 2. Equivalent circuit for basic SCFL cell. the essential characteristics of transistor behaviour, maintaining a good accuracy, but largelysimplifying the calculation.The non-linear equation for the channel current  I  D  determines the accuracy of the model:dierent models have been proposed in the literature for MESFET and HEMT devices [20],to better describe the behaviour of real transistors under dierent bias conditions, obtaining acloser t to the relationship of the drain current as a function of gate-source and drain-sourcevoltages. In this work we have chosen to use the Curtice model [21], where the drain currentin saturation region is given by  I  D  = k  ( V  GS  − V  T ) 2 (1 + V  DS )tanh( V  DS ) (1)More sophisticated models that take into account higher order eects would be intractable for analytical manipulation; however, the results we obtain are quite accurate, and the insightsgained from them are suciently useful to be worth pursuing. Assuming the channel lengthmodulation is negligible, due to the limited output voltage swing, and so neglecting thedependence of the drain current on the drain-source voltage  V  DS , Equation (1) can be written as  I  D  =  ( V  GS  − V  T ) 2 (2)This model is equivalent to the Shichman–Hodges model for MOS transistors [15], so thatthe results of this analysis are valid for MCML gates as well.Figure 2 shows the equivalent circuit for the basic cell we have to study;  C  S  represents thecapacitance associated with the tail current source. Input voltages can be written as V  1  = V  G  + V  a ( t  ) (3) V  2  = V  G  + V  b ( t  ) (4)where  V  G  is the input common-mode voltage and in the most general case  V  a   =  − V  b .Circuit behaviour can be described by considering the voltage  V  S  on the source node of the dierential pair, whence the drain currents can be calculated. From the analysis of thecircuit in Figure 2, and under the hypothesis that transistors never enter the triode region, thefollowing dierential equation can be derived for the source voltage: − ( C  1  + C  2  + C  S )d V  S d t   + (  1  +  2 ) V  2S  − 2(  1 y 1  +  2 y 2 ) V  S  =  F  ( t  ) (5)where y k   = V  k   − V  T  k   =1 ; 2 (6) Copyright  ?  2005 John Wiley & Sons, Ltd.  Int. J. Circ. Theor. Appl.  2005;  33 :365–378  ANALYTIC TRANSIENT SOLUTION OF SCFL LOGIC GATES  369and  F  ( t  )=  I  TAIL  −  1 y 21  −  2 y 22  − C  1 d y 1 d t   − C  2 d y 2 d t   (7)It has to be noted that transconductance coecients   k   and capacitances  C  k   in Equation (5)can be dierent even if geometrical dimensions of the transistors are identical, to take intoaccount the eect of dierent bias conditions. In particular, we put   k   =0 when the transistor enters the cut-o region, to continue using the same equation.For a more general analysis, polynomial expressions of arbitrary maximum exponent areconsidered for all inputs, including the tail current. We can then write y 1 ( t  )= V  G  − V  T  + V  a ( t  )= n  k  =0 a k  t  k  (8) y 2 ( t  )= V  G  − V  T  + V  b ( t  )= n  k  =0 b k  t  k  (9)and for the tail current  I  TAIL ( t  )= n  k  =0 g k  t  k  (10)where  n  is the highest of the orders of the polynomials describing the inputs and the tailcurrent.Equation (5) is a Riccati dierential equation [22], that we can write in a general form asd V  S d t   =  KV  2S  +  P  ( t  ) V  S  + Q ( t  ) (11)where  P  ( t  ) and  Q ( t  ) are polynomials in  t  .The analytical solution of this equation can be expressed in a form containing ConuentHypergeometric Functions [23], that are dened in the complex plane by  M  ( ; ;  z  )= ∞  n =0 (  ) n  z  n (  ) n n ! (12)An alternative, more practical approach, to solve the Riccati equation is the innite power series method [24], that can be shown to have both the absolute and the uniform convergence properties. Stated dierently, if only the rst terms of the series are used to evaluate thesolution, these properties assure that the error is bounded. The power series method can be applied directly to the non-linear equation (12), and since  P  ( t  ) and  Q ( t  ) are analyticfor   t  ∈ [0 ; ∞ ) the solution thus found can be proved to be the correct solution, although itsconvergence radius can be limited [25].According to the innite power series method, a solution of Equation (5) is found in theform V  S ( t  )= ∞  k  =0 q k  t  k  (13) Copyright  ?  2005 John Wiley & Sons, Ltd.  Int. J. Circ. Theor. Appl.  2005;  33 :365–378
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