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Section J7: FET Amplifier Design
The expressions for amplifier characteristics developed in the previous section will now be used in the design process. Remember that for design, it is fundamentally important to understand what it is that you are designing by defining the operational conditions, any constraints (physical or operational) that may exist, what is known and what is unknown. Only
after
a complete understanding has been achieved can the design process be implemented effectively – say it with me now,
don’t just grab equations
!
The CS and SR Amplifier
The circuit for a SR amplifier using an n-channel JFET is given in Figure 6.40a and is reproduced to the right Note that your text describes this amplifier circuit as a common source configuration. The only difference between the SR and CS is the addition of a bypass capacitor (C
S
) across R
S
. As you go through your text, don’t let this confuse you – when your author refers to this configuration as
common source
, he is implying
common source with source resistance
. The following discussion on the design procedure of an SR amplifier holds for JFET and MOSFET devices. It is assumed that a device has been selected and that its characteristics are known. Also assumed is that sufficient information as to the supply voltage(s), load resistance, voltage gain, current gain, and/or input resistances are provided and that the gain requirements are within the range of the transistor being used. This is the same thing we did in our study of BJT amplifier design – and just like then, it is our job as designers to determine the remaining circuit components to satisfy specifications. As we did for BJT design, the first step is to define a Q-point. For convenience, the Thevenin equivalent voltage and resistance and the Q-point relationships developed in Section J4 are repeated here (remember that the assumption |
λ
v
DS
|<<1 in the derivation of these equations):
211212121
R R RV V R R R R R R R
DDGGG
+=+==
||
)()(
)()()()(
JFET V V I V V V I I MOSFET V V I V V KV V V K V V V K I
PGSQ DSS DSQPGSQ DSS DQT GSQ DSS T GSQT T GSQ DSQT GSQ DQ
2222222
111111
⎟⎟ ⎠ ⎞⎜⎜⎝ ⎛ −≅+⎟⎟ ⎠ ⎞⎜⎜⎝ ⎛ −=⎟⎟ ⎠ ⎞⎜⎜⎝ ⎛ −=⎟⎟ ⎠ ⎞⎜⎜⎝ ⎛ −=−≅+−=
λ λ
S DQGSQGG
R I V V
+=
)(
S D DQ DSQS DQ DSQ D DQ DD
R R I V R I V R I V
++=++=
JFETs for V V Note
V V V I g
PT T GSQT DSS m
=⎟⎟ ⎠ ⎞⎜⎜⎝ ⎛ −−=
:
12 A generic family of characteristic curves for an n-channel device is shown to the right. This figure is based on Figure 6.40 of your text, but all specifics as to identifying numbers have been removed. Note that the Q-point mustbe in the saturation region of the curves. As illustrated, definition of the Q-point identifies the operational conditions V
DSQ
, V
GSQ
and I
DQ
. Assuming we have been given sufficient information as to V
DD
, R
L
, gain(s) and R
in
, our task is to define R
S
, R
D
, R
1
and R
2
. R
1
and R
2
are defined once V
GG
and R
G
are determined, so we’ll go along with your author and solve for R
S
and R
D
first. We will be (somewhat) following your text’s derivations, since it cannot be stressed enough that the resulting equations may have assumptions and/or constraints that must be followed. Writing the dc KVL around the drain source loop in the figure above (assuming I
S
I
D
) and solving for the unknown resistors R
S
and R
D
yield one equation in two unknowns:
1
K I V V R R
D DS DD DS
=−=+
, (Equation 6.59)
where the constant K
1
is introduced to simplify future notation. Note that we need another equation to solve for the resistances (two unknowns requires two independent equations). For our second equation, we can use either the voltage gain or current gain expression derived in the previous section:
mS L DS m L DmV
g R R R Rg R Rg A
/)||()()||(
11
+−=+−=
L D DmS Gi
R R Rg R R A
++−=
/
1 The trick here is to realize that
DS
RK R
−=
1
or
S D
RK R
−=
1
and substitute into one of the gain equations (where
K
1
=(V
DD
-V
DS
)/I
D
from Equation 6.59). When this approach is taken, the gain equation has only one unknown and may be solved. To follow your text, if we use the voltage gain equation and substitute for R
S
, the resulting equation becomes:
m D L DV
g RK R R A
/)()||(
1
1
+−−=
. (Equation 6.60) Solving this equation for R
D
results in the quadratic equation 0) /1() / /1(
112
=+−−−+−
LmDv LLmD
RgK R ARRgK R
. There are two possible solutions to the quadratic equation, one negative and one positive. Since R
D
must be greater than zero, only the positive solution is used. However, it’s not quite that simple and we must get through
checkpoint #1
…
If the positive solution of the quadratic results in
R
D
> K
1
(recall that R
S
=K
1
-R
D
and K
1
=(V
DD
-V
DS
)/I
D
), a negative value for R
S
results. If this happens, a new Q-point must be selected (i.e., start all over).
If the positive solution results in a
positive R
S
, we’re good to go and can proceed as follows. With R
S
and R
D
known, the remaining unknowns are R
1
and R
2
. Directly analogous to our work with BJT amplifiers, the first thing we do is write the general dc KVL for the gate source loop to solve for V
GG
:
S DGS GG
R I V V
+=
. (Equation 6.62) Once a value for V
GG
is obtained, we hit
checkpoint #2
…
if V
GG
has the
same polarity
as V
DD
, use either the equation for input resistance or current gain (reproduced below) to solve for R
G
.
21
R R R R
Gin
||
==
L D DmS Gi
R R Rg R R A
++−=
/
1 Using the expressions for the Thevenin equivalent voltage and resistance, we can now
solve for R
1
and R
2
:
GG DDG DDGGG
V V R RV V R R
=−=
21
1
/
. (Equation 6.63)
And we’re done!
Otherwise,
if V
GG
has the
opposite polarity
of V
DD
, it is not possible to directly solve for R
1
and R
2
(since both R
1
and R
2
must be positive and greater than R
G
). In this case, a rule of thumb is to
let V
GG
=0V
. This means that
∞→
2
R
(reference the equation above), and
G
R R
=
1
. However, the value of R
S
now needs to be modified to ensure that Equation 6.62 is equal to zero, which is direct contradiction to the solution of the quadratic we started with!
Oh well, can’t do it right? Come now, you’ve been at this long enough to know that there’s a trick involved!
The solution to these conflicting requirements is illustrated in Figure 6.41 of your text and is shown to the right. This is the same n-channel JFET CS amplifier we started with, but now the source resistance is split and part of it is bypassed by the capacitor C
D
. Using our standard assumption that the capacitor is open to dc and a short for the operational frequency range, we get
1
S acS
R R
21
S S dcS
R R R
=+=
;
. Going back to our dc KVL equation for the gate-source loop and setting V
GG
equal to zero, we can define R
Sdc
:
Sdc DGS GG
R I V V
+==
0, and (Equation 6.64)
DGS Sdc
I V R
−=
.

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