Documents

12~chapter 07 diagnosis

Description
VLSI Test
Categories
Published
of 80
All materials on our website are shared by users. If you have any questions about copyright issues, please report us to resolve them. We are always happy to assist you.
Related Documents
Share
Transcript
  EE141 1   VLSI Test Principles and ArchitecturesCh. 7 -Logic Diagnosis -P. 1 Chapter 7 Chapter 7  Logic DiagnosisLogic Diagnosis  EE141 2   VLSI Test Principles and ArchitecturesCh. 7 -Logic Diagnosis -P. 2 OutlineOutline  Introduction  Combinational Logic Diagnosis  Scan Chain Diagnosis  Logic BIST Diagnosis  Conclusion  EE141 3   VLSI Test Principles and ArchitecturesCh. 7 -Logic Diagnosis -P. 3 What would you do when chips fail? What would you do when chips fail?   Is it due to design bugs?  If most chip fails with the same syndrome when running an application  Is it due to parametric yield loss?  Timing-related failure?  –  Insufficient silicon speed?  Noise-induced failure?  –  supply noise, cross-talk, leakage, etc.?  Lack of manufacturability?  –  inappropriate layout?  Is it due to random defects?  Via misalignment, Via/Contact void, Mouse bite,  Unintentional short/open wires, etc.  EE141 4   VLSI Test Principles and ArchitecturesCh. 7 -Logic Diagnosis -P. 4 Problem: Fault DiagnosisProblem: Fault Diagnosis CircuitUnderDiagnosis(CUD) test patterns = expected responsefaulty response not equal ! Question: Where are the fault locations ? a chip with defects inside This chapter focuses more on diagnosis of defects or faults, notdesign bugs 
We Need Your Support
Thank you for visiting our website and your interest in our free products and services. We are nonprofit website to share and download documents. To the running of this website, we need your help to support us.

Thanks to everyone for your continued support.

No, Thanks