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Chapter 12 Test Technology Trends in Nanometer Age 1 VLSI Test Principles and Architectures EE141 Ch. 12 - Test Technology Trends In Nanometer Age - P. 1 What is this Chapter About? Introducethe test technology roadmap Focus on a number of difficult challe
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  EE141 1   VLSI Test Principles and ArchitecturesCh. 12 -Test Technology Trends In Nanometer Age - P. 1 Chapter 12 Chapter 12  Test Technology Trends Test Technology Trends in Nanometer Agein Nanometer Age  EE141 2   VLSI Test Principles and ArchitecturesCh. 12 -Test Technology Trends In Nanometer Age - P. 2 What is this Chapter About? What is this Chapter About?   Introduce the test technology roadmap  Focus on a number of difficult challenges and test solutions:  Delay testing, Physical failures and Soft errors, FPGA testing, MEMS testing, High-speed I/O testing, and RF testing  Concluding remarks  EE141 3   VLSI Test Principles and ArchitecturesCh. 12 -Test Technology Trends In Nanometer Age - P. 3 Section 12.1Section 12.1 Test Technology RoadmapTest Technology Roadmap  EE141 4   VLSI Test Principles and ArchitecturesCh. 12 -Test Technology Trends In Nanometer Age - P. 4 Moore’s Law and Test ChallengesMoore’s Law and Test Challenges  Moore’s law: the number of transistors integrated per square inch will double approximately every 18 months.  To keep track of Moore’s law: die size , feature size , gate delay , interconnect delay  To reduce interconnect delay, interconnects are made taller and taller, and this causes crosstalk noises between adjacent lines due to capacitive and inductive coupling (called signal integrity problem). This is very difficult to test.
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