Documents

4 lala.pdf

Description
la
Categories
Published
of 4
All materials on our website are shared by users. If you have any questions about copyright issues, please report us to resolve them. We are always happy to assist you.
Related Documents
Share
Transcript
  Digital Circuit Testing and Testability Parag  K.  ala Ekctncal Enginecnng IVpartmcrt Nonh Caiottna Agncultural ind Tecimical Stale Univrixity Greensboro.  Nocih  Carolina /\ voli^^ ACADEMIC  PRESS SnDicfo Loodoa Ne Yoft Sydiwy  Tokyo  T«  ConttMits Prrfacr Td C^hHptor  I  I aulis  in  Diiiiial irvuils II I: 1^ lailuirs Athl l«ultN M»Mlohn>;  til  |-.iuli\ I  .J  I  SlUik  \t  l;Ull|v 1.2.2  l(nd>:in):  I  ;iuti\ 1.2,^  \i}VAk\  MKI  IransiMoi Ntuik <>n  i \x^»  I  MUIIN  in  CMOS I  :-l IVI.n I.mils roni|HM;US  I  .UltlN RclciriK CH I I 2 u> 11 14 IT C  hiipltj*  2  lost  iciictiMion  lot  (\>mbin.iiioniil  I  o^w  Ctf\\u\\ I 1» 1  .uih  |)KI|,-U««MN  OI  l)|>£llitl i livuilx ICKl (tCltOtNllOll ll\hlUt)U<*« l«M l\MUtMltlthtMUlt ClIV Ull> *  2  I  (>lh*  OlIlh-MMOIIill  Path  SdlMlUAlHMI I*IM>I  M  \V U  i hwtWtexi  IkMMi^* MAm^* I \N (laihHil i»iH nlfNl Ir^i  (it  n.i.iiitmt I  V U\  I  mill  I  VU\lHMt I K  t.  V ll.m Ol  Mllllipll I  null*  til I »MII*Hlldll*MWl I t^K t  HXUll* ^ 20 » il t :ã M 47 4 » Vil  55 v ii  Contents Chapter  3 Testable  Combinational  Logic Circuit Design 3 1  The  Reed-Muller  Expansion Technique 3.2 Three-Level  OR-AND-OR  Design  53 3.3 Automatic  Synthesis  of Testable  Loeic '** 3.4 Testable Design of Multilevel Combinational Circuits  ^ 3 4 1  Single Cube Extraction  ^ 3.4.2 Double Cube Divisor  ^ 3.4.3 Extraction of a Double Cube Divisor and Its Complement  « 3.5 Synthesis of Random  Panem  Testable  Combmational  Circuits  Z 3.6 Path  Delav  Fault Testable Combinational Logic Design   3.7 Testable PLA Design  '^ References 77 Chapter 4  Test Generation for Sequential Circuits  79 4 1  Testing of Sequential Circuits as Iterative Combinational Circuits 79 4.2 State Table Verification  gj 4.3 Test Generation Based on Circuit Structure  87 4.4 Functional Fault Models  92 4.5 Test Generation Based on Functional Fault Models 94 References  100 Chapter  5 Design of Testable Sequential Circuits  101 5 1  Controllability and  Obser\ability  1^1 5.2 Ad Hoc Design Rules for Improving Testability 1^ 5.3 Design of Diagnosable Sequential Circuits 5.4 The Scan-Path Technique for Testable Sequential Circuit Design 5.5 Level-Sensitive Scan Design  (LSSD) 5 5 1  Clocked Hazard-Free Latches 5.5.2 LSSD Design Rules 5.5.3 Advantages of the LSSD Technique 107 110 114 114 116 121 122 5.6 Random Access Scan Technique  ^5 5.7 Partial Scan  p-^ 5.8 Testable Sequential Circuit Design Using Nonscan Techniques  ^'^ 5.9 Crosscheck  133 5 10  Boundary- Scan  I3jl References 140 Chapter 6  Built-in Self Test 141 6 1  Test Panem Generation for BiST  141 6 1 1  Exhaustive Testing  |43 6 1 2  Pseudo-Exhaustive Pattem Generation  Contents 6 L3  ^^udo-Random Pattem  Generator G I 4  Deterministic Testing  ,^ 6.2 Output Response Analysis  S\ 6 2 1  Transition Count  ,„ 6.2.2 Syndrome Checking 6.2.3 Signature Analvsis 6.3 Circular BIST 6.4 BIST Architectures  15<) 6.4.1 BILBO  Built-In  Logic Block  Observer*  » 6 4 2 —^. u.v^i^.  \7ijMrivcri  Chapter 7  Testable Memory Design x 153 153 154 155 62 6.4.3 LOCST LSSD On-Chip Self-Test)  *^^ References 165 66 169 7.1 RAM Fault Models 69 7.2 Test  Algorithms  for RAMs  .^2 7 2 1  GALPAT Galloping Os and Is)  172 7.2.2  Walking  Os and  Is 173 7.2.3 March Test  173 7.2.4 Checkerboard Test  174 7.3 Detection of Pattern-Sensitive Faults  174 7.4 BIST Techniques for RAM Chips  179 7.5 Test Generation and BIST for Embedded RAMs  184 References  191 Appendix  Markov Models  ^ ^ Index 195
We Need Your Support
Thank you for visiting our website and your interest in our free products and services. We are nonprofit website to share and download documents. To the running of this website, we need your help to support us.

Thanks to everyone for your continued support.

No, Thanks