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74HC_HCT93_CNV_2

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  D T SHEET Product specificationFile under Integrated Circuits, IC06December1990 INTEGRATED CIRCUITS  74HC/HCT93 4-bit binary ripple counter For a complete data sheet, please also download: ã The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications ã The IC06 74HC/HCT/HCU/HCMOS Logic Package Information ã The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines  December19902 Philips SemiconductorsProduct specification 4-bit binary ripple counter74HC/HCT93 FEATURES ã Various counting modes ã Asynchronous master reset ã Output capability: standard ã I CC  category: MSI GENERAL DESCRIPTION The 74HC/HCT93 are high-speedSi-gate CMOS devices and are pincompatible with low power SchottkyTTL (LSTTL). They are specified incompliance with JEDEC standardno.7A.The 74HC/HCT93 are 4-bit binaryripple counters. The devices consistof four master-slave flip-flopsinternally connected to provide adivide-by-two section and adivide-by-eight section. Each sectionhas a separate clock input (CP 0  andCP 1 ) to initiate state changes of thecounter on the HIGH-to-LOW clocktransition. State changes of the Q n outputs do not occur simultaneouslybecause of internal ripple delays.Therefore, decoded output signalsare subject to decoding spikes andshould not be used for clocks orstrobes.A gated AND asynchronous masterreset (MR 1  and MR 2 ) is providedwhich overrides both clocks andresets (clears) all flip-flops.Since the output from thedivide-by-two section is not internallyconnected to the succeeding stages,the device may be operated in variouscounting modes. In a 4-bit ripplecounter the output Q 0  must beconnected externally to inputCP 1 .The input count pulses are applied toclock inputCP 0 . Simultaneousfrequency divisions of 2, 4, 8 and 16are performed at the Q 0 , Q 1 , Q 2  andQ 3  outputs as shown in the functiontable. As a 3-bit ripple counter theinput count pulses are applied to inputCP 1 .Simultaneous frequency divisions of2, 4 and 8 are available at the Q 1 , Q 2 and Q 3  outputs. Independent use ofthe first flip-flop is available if the resetfunction coincides with reset of the3-bit ripple-through counter. QUICK REFERENCE DATA GND=0 V; T amb =25  ° C; t r =t f =6 ns Notes 1.C PD  is used to determine the dynamic power dissipation (P D  in  µ W):P D =C PD  × V CC2 × f i  + ∑ (C L  × V CC2 × f o ) where:f i =input frequency in MHz; f o =output frequency in MHz ∑ (C L  × V CC2 × f o )=sum of outputsC L =output load capacitance in pF; V CC =supply voltage in V2.For HC the condition is V I =GND to V CC ; for HCT the condition is V I =GND to V CC  − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”  . SYMBOLPARAMETERCONDITIONSTYPICALUNITHCHCT t PHL  / t PLH propagation delayCP 0  to Q 0 C L =15 pF; V CC =5 V1215nsf max maximum clock frequency10077MHzC I input capacitance3.53.5pFC PD power dissipation capacitance per packagenotes 1 and 22222pF  December19903Philips SemiconductorsProduct specification 4-bit binary ripple counter74HC/HCT93 PIN DESCRIPTIONPIN NO.SYMBOLNAME AND FUNCTION 1CP 1 clock input 2 nd , 3 rd  and 4 th  section (HIGH-to-LOW, edge-triggered)2, 3MR 1 , MR 2 asynchronous master reset (active HIGH)4, 6, 7, 13n.c.not connected5V CC positive supply voltage10GNDground (0 V)12, 9, 8, 11Q 0  to Q 3 flip-flop outputs14CP 0 clock input 1 st  section (HIGH-to-LOW, edge-triggered)Fig.1 Pin configuration.Fig.2 Logic symbol.Fig.3 IEC logic symbol.  December19904Philips SemiconductorsProduct specification 4-bit binary ripple counter74HC/HCT93 Fig.4 Functional diagram.Fig.5 Logic diagram. FUNCTION TABLENotes 1.Output Q 0  connected toCP 1 .H=HIGH voltage levelL=LOW voltage level MODE SELECTIONCOUNTOUTPUTSQ 0 Q 1 Q 2 Q 3 0123LHLHLLHHLLLLLLLL4567LHLHLLHHHHHHLLLL891011LHLHLLHHLLLLHHHH12131415LHLHLLHHHHHHHHHH RESETINPUTSOUTPUTSMR 1 MR 2 Q 0 Q 1 Q 2 Q 3 HLHLHHLLLLLLcountcountcount
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