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Reg. No. :
B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011 Third Semester Electronics and Communication Engineering EC 2203 — DIGITAL ELECTRONICS (Regulation 2008) (Common to PTEC 2203 Digital Electronics for B.E. (Part-Time) Electronics and Communication Engineering Third Semester – Regulation 2009) Time : Three hours Maximum : 100 marks Answer ALL questions PART A — (10
×
2 = 20 marks) 1.
State DeMorgan’s theorem. 2.
What is a totem output? 3.
Write the logic expressions for the difference and borrow of a half subtractor. 4.
Design a single bit magnitude comparator to compare two words A and B. 5.
Write the characteristic equation of a JK flip flop. 6.
State the differences between Mealy and Moore State machines. 7.
What is the difference between PAL and PLA? 8.
Implement the exclusive-or function using ROM. 9.
What are the basic building blocks of a Algorithmic state machine chart? 10.
What are the two types of Asynchronous sequential circuits? PART B — (5
×
16 = 80 marks) 11.
(a) (i) Express the Boolean function
C B A F
′+=
in a sum of minterms. (6) (ii) Simplify the Boolean function using K-map
( ) ( )
14,13,12,9,8,6,5,4,2,1,0,,,
Σ=
z y xw F
(10)
Question Paper Code :
11280
4 2 1 4 2 1 4 2 1
11280
2Or (b) (i) Simplify the following Boolean function by using a Quine-McCluskey method.
( ) ( )
13,12,10,8,7,6,3,2,0,,,
m DC B A F
Σ=
(8) (ii) Draw the schematic and explain the operation of a CMOS inverter. Also explain its characteristics. (8) 12.
(a) (i) Design a full Adder using two half adders and an OR gate. (6) (ii) Explain the operation of a BCD Adder. (10) Or (b) (i) Draw the logic diagram of a 2-bit by 2-bit binary multiplier and explain its operation. (8) (ii) Implement the following function using suitable multiplexer
( ) ( )
15,14,13,12,11,4,3,1,,,
Σ=
DC B A F
(8) 13.
(a) (i) Convert D flip flop to T flip flop. (6) (ii) Design a serial binary adder. (10) Or (b) (i) Explain the operation of a BCD ripple counter with JK flip flops.(8) (ii) Design a clocked sequential machine using T flip-flops for the following state diagram. (use straight binary assignment). (8) 14.
(a) (i) Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number. (10) (ii) Briefly explain the EPROM and EEPROM technology. (6) Or
4 2 1 4 2 1 4 2 1
11280
3
(b) (i) Implement the following functions using 3 input, 4 product term and 2 output PLA
C B A AC B A F
′′++′=
1
( )
′+=
BC AC F
2
(8) (ii) With logic diagram, explain the basic macrocell. (8) 15.
(a) (i) Draw the ASM chart for the following state diagram. (8) (ii) Design the following synchronous sequential circuit using D flip flop and logic gates. (8) Or (b) What is an Hazard? What are the types of hazards? Check whether the following circuit contains an hazard or not
3221
x x x xY
′+=
If the hazard is present, demonstrate its removal. (16) ————————
4 2 1 4 2 1 4 2 1

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