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Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture

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Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture
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  Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture Jin Hyuk Yoon, Eyee Hyun Nam, Yoon Jae Seong,Hongseok Kim, Bryan S. Kim, Sang Lyul Min, and Yookun ChoIEEE Computer Architecture Letters, Vol. 7, No. 1 Aug. 5, 2008Speaker: Sehwan Lee  Introduction Chameleon SSD(NAND flash memories) + Ferroelectric RAM FRAM Non-volatileFast random readsIn-place-updates  Chameleon Hybrid SSD Architecture Chameleon SSD Architecture Overview    Chameleon Hybrid SSD Architecture Chameleon SSD Architecture Overview   FPGA  Two Types of Non-volatile Data in Chameleon Data blocksWrite buffers Block-level write buffers To optimize the performance of sequential writes from the host  Page-level write buffers To optimize the performance of small random writes from the host  Chameleon Hybrid SSD Architecture
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