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  COM203P Introduction to Computer Organization Practice Project Work 1 Problem Statement Design single core 64-bit processor with the following specifications. ã  32-numbers of 64-bit registers. ã  Three internal bus based processors, where bus A and bus B as input ports to the ALU and bus Cis connected to output of ALU. ã  Design 64-bit logic and unsigned arithmetic circuit. ã  Design Single precision floating point unit. ã  Design 64-bit Logic unit. ã  Design Load and Store unit. ã  Processor has 64-bit data line and 22-bit address line. ã  Instruction format size is 32-bit. ã  Instruction register size is 32-bit and Program counter size is 22-bit. 2 Design Approach 2.1 Logic and Arithmetic Circuit Design Design the logic and arithmetic circuits as follows: 2.2 Addition Design 64-bit Carry Lookahead Adder circuit using KGP blocks and Recursive doubling algorithm. Nowuse the same module for the design of the addition, addition with carry, subtraction and subtraction withbarrow modules. 2.3 Multiplication Design the 64-bit Wallace Tree multiplier (or Array multiplier) using carry-save-adders. 2.4 Floating Point Arithmetic Unit Design Single precision floating addition, subtraction and multiplication circuit, where adder can be de-signed using carry lookahead adder and multiplier can be either Wallace tree multiplier or Array multiplier. 3 Instruction format and Encoding 3.1 Instruction Format The design instruction should of 32-bit size. Load and Store Instruction will have the format as shown inFigure 1. The rest of the logic and arithmetic instructions will have the format as shown in Figure 2.  Figure 1: Instruction format for Load and Store InstructionsFigure 2: Instruction format for Arithmetic and Logic Instructions 3.2 Operation code Encoding Encode the instruction opcode as follows: Operation Description UsageCode 00000 Addition  ADDR dst ,R src 2 ,R src 1 00001 Addition with carry  ADCR dst ,R src 2 ,R src 1 00010 Subtraction  SUBR dst ,R src 2 ,R src 1 00011 Subtraction with Barrow  SBBR dst ,R src 2 ,R src 1 00100 Multiplication  MULR dst ,R src 2 ,R src 1 00101 Floating Point Addition (Single Precision)  FADDR dst ,R src 2 ,R src 1 00110 Floating Point Subtraction (Single Precision)  FSUBR dst ,R src 2 ,R src 1 00111 Floating Point Multiplication (Single Precision)  FMULR dst ,R src 2 ,R src 1 01000 Logical bit wise AND  ANDR dst ,R src 2 ,R src 1 01001 Logical bit wise OR  ORR dst ,R src 2 ,R src 1 01010 Logical bit wise XOR  XORR dst ,R src 2 ,R src 1 01011 Logical bit wise NAND  NADDR dst ,R src 2 ,R src 1 01100 Logical bit wise NOR  NORR dst ,R src 2 ,R src 1 01101 Logical bit wise XNOR  XNORR dst ,R src 2 ,R src 1 01110 Logical NOT  NOTR dst ,R src 1 01111 Negation (twos complement value)  NEGR dst ,R src 1 10000 Load  LOADR dst ,Address (22  − bit )11000 Store  STORER dst ,Address (22  − bit ) 4 Processor Architecture The designed processor architecture is as shown in the Figure 3.  Figure 3: Processor Architecture
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