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Design and Optimization of a Low Complexity All- Digital Digital-to-Analog Converter Marcel Siadjine Njinowa, Hung Tien Bui Department of Applied Sciences Université du Québec à Chicoutimi {msiadjine, ht2bui}@uqac.ca François-Raymond Boyer Department of Computer Engineering École Polytechnique de Montréal Francois-R.Boyer@polymtl.ca Abstract—This paper presents a novel all-digital circuit topology for a digital-to-analog converter (DAC). It consists of ser
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    Design and Optimization of a Low Complexity All-Digital Digital-to-Analog Converter Marcel Siadjine Njinowa, Hung Tien Bui Department of Applied Sciences Université du Québec à Chicoutimi {msiadjine, ht2bui}@uqac.ca François-Raymond Boyer Department of Computer Engineering École Polytechnique de Montréal Francois-R.Boyer@polymtl.ca  Abstract   —This paper presents a novel all-digital circuit topology for a digital-to-analog converter (DAC). It consists of series of inverters whose outputs are connected together. Depending on the thermometer code input, some inverters will have conducting PMOS whereas others will have conducting NMOS, thus providing an analog output. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. Due to process and temperature variations, the proposed DAC has a resolution that is limited to 3 bits in a 0.18   m CMOS technology. Transistor-level simulations using Cadence’s Spectre simulator have also been done to validate the theoretical results. I.   I  NTRODUCTION  Over the years, significant research activities have been dedicated to the design of DACs, which are essential components in modern applications such as video signal  processing, digital signal synthesis, and both wired and wireless transmitters [6], [7], [8], [9]. There have been many examples of DACs reported in literature [1], [4], [5]. Each has its own merits and uses techniques such as voltage division, current steering and charge scaling to map the digital value into an analog quantity. While many approaches have been developed to improve speed, linearity and resolution, not much effort has been put into making DACs implementable using digital technologies. The advantages of using digital technologies include  benefiting from the mature automated design flow, powerful verification techniques and easy prototyping using FPGAs. This paper presents a low resolution all-digital circuit topology for a DAC that can be implemented using only standard cells. Such approach can make the design process simpler and improve the time to market. The outline of the paper is as follows. In Section II, the implemented DAC architecture is presented, while in Section III the optimization procedure to reduce non-linearity is explained. Section IV presents the simulation results and finally, conclusions are formulated in section V. II.   DAC   A RCHITECTURE  The architecture of the proposed DAC is shown in Fig. 1 a) and b). It consists of  X   buffers whose inputs are driven by digital signals and whose outputs are connected together. The operation of the DAC depends on the number of buffers driving ‘1’ and the region of operation of the transistors. The input of the DAC is in thermometer code and therefore, the minimum number of buffers required for a Y  -bit resolution is 2 Y  -1 . Even though there is a minimum number of buffers, there is no maximum. It is possible to use more than 2 Y -1 gates by connecting several buffer inputs together. This is  particularly useful when trying to improve the linearity of the DAC, as we will discuss in Section III. In the final implementation, however, the total number of independent inputs must be 2 Y  -1 . D 0 D 1 D 2 D M-2 D M-1   D 0 D 1 D 2 D X-2 D X-1  a) b) Fig 1. Architecture of the Proposed DAC at the a) Gate Level and at the b) Transistor Level The functionality of the proposed DAC can be understood as follows. When the input bits of the DAC are all ‘0’, all  buffer outputs will be ‘0’ and therefore, the DAC output will also be ‘0’. Similarly, when the input signals are all ‘1’, the output of the DAC will be ‘1’. When some inputs are ‘0’ while others are ‘1’, the output voltage will be somewhere between supply and ground voltages. Even though the output voltage is not expected to be proportional to the number of ‘1’ at the input, it will be a monotonic function. To find the input-output relationship of this DAC, it is possible to analyze the transistor-level circuit. Consider the 2-bit DAC shown in Fig. 2. Fig 2 a) shows the general schematic of the DAC. When analyzing the output voltage, it is only necessary to analyze the behavior of the inverters connected to the output. The circuit in Fig. 2 b) shows the same circuit with a sample input “110” whereas Fig. 2 c) shows only the conducting transistors that are present at the output node when the input is “110”. To calculate the output voltage of the DAC, we will need to find the drain   voltages V   D  that makes the current through the PMOS equal to the current through the NMOS. D 0 D 1 D 2   110   001  a) b) c)  Fig.2. 2-bit DAC Configuration a) with Generic Inputs, b) when the Input is “110” and c) when Only Showing the Conducting Transistors  The equation of the drain current depends on the region of operation of the conducting transistors. These transistors can operate in either triode or saturation. Since the V  GS   and the V   DS   of all conducting PMOS transistors are equal, all PMOS transistors will operate in the same region. A similar reasoning applied to the NMOS transistors also allows us to conclude that all conducting NMOS will operate in the same region. With two possible regions of operation for each type of transistor, there is a total of four possibilities: triode-saturation, triode-triode, saturation-triode and saturation-saturation. The fourth case, the case of saturation-saturation, will not be taken into account since it only occurs when the threshold voltage of the transistors is very large with respect to the supply voltage. For instance, assuming that the threshold voltage ( V  TH  ) of the NMOS and that of the PMOS are equal, V  TH   would have to be larger than VDD/2  for the case of saturation-saturation to occur. This is a rare occurrence and is therefore not considered. Assuming, once again, that V  TH   is the same for both transistor types, the region of operation of the transistors depends on V   D , as shown in Fig 3. VDDVSSVDD-V TH VSS+V TH V D P: TriodeN: SaturationP: TriodeN: TriodeN: TriodeP: Saturation   Fig. 3. Transistor Operation Regions  In steady-state, the current supplied through the P-network is equal to the current flowing through the N-network. Considering this relation, we can derive an equation for the DAC output by writing the current equations and solving for V   D : )1( )()(  D N  D P  V  I V  I   =  In (1),  I   P   and  I   N   are the currents that vary as a function of V   D . Depending on their region of operation, these functions can change. For instance, when the DAC operates in triode-triode region, the current through the PMOS and NMOS networks are respectively: ( ) )2(2|| 2  −−= SDSDTH SGOX  P  P  V V V V  LW C  M  I   µ    ( ) ( ) )3(2 2  −−−=  DS  DS TH GS OX  N  N  V V V V  LW C  M  N  I   µ   In (2) and (3),  N   is the total number of buffers whereas  M   is the number of buffers whose output is ’1’.To simplify the notation, we will replace  µ  C  OX  (W/L)  by  K   and consider that  K   is the same for both transistor types. Knowing that the current through the PMOS and NMOS networks is the same, the following expression can be obtained: ( ) [ ]  ( ) ( ) [ ] ( ) )4(0 222 22 =      −−+−−−+− − VDDVDDV VDD MK  V V VDD K  M  N V  MK V  MK  K  M  N  TH  P  DTH  N TH  P  D P  N   To find the output voltage of the DAC, one needs to solve for V   D  in the quadratic equation shown in (4) and validate that the value of V   D  puts both transistor types in the triode region. Using the same technique, one can derive the following equations for the triode-saturation and saturation-triode mode of operation, respectively given by (5) and (6): ( )( )( ) )5(0 ]2[22 222 =−−+−−−− TH  DD N  DD DDTH  DD p DTH  p D p V V  M  N  K  V V V V  MK V V  MK V  MK    ( ) ( )( ) ( ) )6(02 22 =−+−−−− TH  DD p DTH  DD N  D N  V V  MK V V V  M  N  K V  K  M  N   To validate the functionality of the proposed DAC, a sample 3-bit design was created. We chose to use twenty-one  buffers, where each thermometer code input bit is connected to three buffers as shown in Fig. 4. D 0 D 1 D 6 013242021195  Fig. 4. Architecture of the 3-bit DAC with Twenty-One Buffers The input-output relationship of the DAC was calculated by solving for V   D  in (4), (5) and (6) and verifying the region of operation of both transistor types. These values of V   D  have  been plotted and are shown in Fig 5. The input-output relationship of the ideal DAC is also shown in the figure as a dotted line. 0 1 2 3 4 5 6 700.20.40.60.811.21.41.61.8  Fig. 5. Output of an Ideal DAC and that of the Proposed DAC To characterize the linearity of the DAC, we used the sum of squared error between the real and ideal output. In this sample implementation, the sum of squared error is calculated to be:    ( ) 1744.0 2 =−=   n DnnIDEAL V V  Error   In this equation, n  is the input whereas V  nIDEAL  and V   Dn  are respectively the ideal and real output. III.   O PTIMIZATION  As seen in Fig. 5, the proposed DAC has a highly non-linear relationship. In order to reduce this non-linearity, we can perform mathematical optimization. The metric used for this work is the squared error difference between the real output and the ideal output. The purpose of our optimization is to minimize this squared error. To do so, we will iteratively change the number of conducting buffers until the difference  between the DAC output and the ideal output is minimized. The heuristic algorithm is described in the following pseudo-code: NumberBuffer(i) = 1 ∀ iFor i=0 to 7 set NumberBuffer(i) ∈  [1, 21] to minimize (ideal(i)   dacvout(i, NumberBuffer)) 2 End  To test the effectiveness of the proposed optimization algorithm, we decided to linearize the 3-bit twenty-one buffer DAC proposed in the previous section. Through this process, we measured the squared errors and plotted the result for each of the input possibilities in Fig 6. 0 5 10 15 20 2500.511.522.5 0 5 10 15 20    2500.20.40.60.811.21.41.61.8   a) Input Code : 0000001 b) Input Code : 0000011 0 5 10 15 20 2500.20.40.60.811.21.40 5 10 15 20 2500.10.20.30.40.50.60.70.80.91   c) Input Code : 0000111 d) Input Code : 0001111   0 5 10 15 20 2500.20.40.60.811.21.41.6   0 5 10 15 20 2500.511.522.5   e) Input Code : 0011111 f) Input Code : 0111111 Fig.6. Squared Error of the Twenty One Buffer 3-bit DAC These figures show the evolution of the squared error as we change the number of buffers being turned ON for a given input. Using this data, we can decide on how to connect the different buffers. Looking at Fig. 6 a), we see that, when the input is 00000001, five buffers should be driving ‘1’ in order to minimize the error. When the input is 00000011, eight  buffers should be driving ‘1’ in order to minimize the error. The other plots of Fig 6 show us how the remaining buffers should be connected. Using this configuration, the DAC output was calculated and the results are shown in Fig 7. It shows a relation that is much more linear when compared to the diagram of Fig. 5. 0 1 2 3 4 5 6 700.20.40.60.811.21.41.61.8   Fig.7. Output of the Optimized DAC To quantify the linearity, we used the sum of squared error and found   ( ) 0062.0 2 =−=   n DnnIDEAL V V  Error   This error is about 3.5 % of its srcinal value and validates the approach used during the optimization process. IV.   T RANSISTOR  -L EVEL D ESIGN  The proposed DAC was designed using 0.18 µ m CMOS technology and simulated using Cadence’s Spectre simulator. The simulation was done for the straight-forward design where buffers were connected three at a time (Fig. 4) and for the case of the optimized design that was proposed in the last section. Fig. 8 a) shows the output of the unoptimized DAC when the input was an incrementing count whereas Fig. 8 b) shows the optimized design stimulated with the same input sequence. The response gives us an indication that the optimized design is more linear than the non-optimized one. a)  b) Fig.8. Response of the a) Unoptimized DAC and that of the b) Optimized DAC     Using these simulation results, we measured the voltages associated to each input value to illustrate the non-linearity of the simulated circuits. This is shown in Fig. 9. In this figure, the dotted line is the ideal response, the solid line with the markers is the unoptimized design whereas the remaining trace is the optimized design. It shows that the optimized design helps obtain a much more linear response. 0 1 2 3 4 5 6 700.511.5   Fig.9. Response of the proposed DAC to a ramp signal  The circuit was also simulated using Monte Carlo analysis for 1000 cycles with both process variation and mismatch analysis. The measured parameter is V   D  to observe its variability when faced with process variations and device mismatch. Under the previously reported conditions and after 1000 simulation cycles, the largest standard deviation observed was about 78mV. It is worth noting that the largest variations occur when the output voltage is near VDD/2 . With 1000 simulation cycles, the maximum peak-to-peak variation was measured to be just under 300mV, which is a little over 1 LSB with supply voltage of 1.8v and a 3-bit configuration. V.   C ONCLUSION  In this paper, we proposed an all-digital circuit topology for a low-resolution DAC. Using basic current equations, we were able to show proper functionality of the proposed design even though the linearity was poor. To solve this problem, a linearization heuristic based on the sum of squared errors was  proposed. In a sample 3-bit twenty-one buffer implementation, the optimization procedure was able to reduce the non-linearity error to 3.5% of its unoptimized value. To validate the results, transistor level simulations have been executed using Cadence’s Spectre simulator. Transient simulations confirm the improvements offered by the optimization process while Monte Carlo simulations show that a 3-bit resolution may be possible in 0.18 µ m CMOS technology. R  EFERENCES   [1]   R. Jacob Baker,  “ CMOS circuit design, Layout, and Simulation ” , 2 nd  Edition,  IEEE Press Series on Microelectronics System.  [2]   J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12-bit intrinsic accuracy high-speed CMOS DAC, ”  IEEE J. Solid-State Circuits , Vol. 33, no. 12, pp.1959-1969, Dec.1998 [3]   Xu Lu, P.Palmers,S.J. Steyaert, “A 130 nm CMOS 6-bit Full Nyquist 3GS/s DAC”,  IEEE J. solid-state circuits, vol..43, Nov 2008,pp.2396-2403 [4]   K. O’Sullivan, C. Gorman, M. Hennessy, V. Callaghan, “A 12-bit 320-MSample/s Current-Steering CMOS D/A Converter in 0.44 mm 2  ”,  IEEE J. solid-state circuits, vol..39, July 2004,pp.1064-1072   [5]   S. Park, G. Kim, S.-C. Park, W. Kim, “A Digital-to-analog Converter Based on Differential-Quad Switching,”  IEEE J. solid-state circuits, vol. 37, no. 10, pp.1335-1338, Oct.2002. [6]   C.-H. Lin and K. Bult, “A 10-b 500-Msamples/s CMOS DAC in 0.6 µ m”,  IEEE J. solid-state circuits , vol. 33, no.12, pp.1948-1958, Dec.1998. [7]   A. Abrial, J. Bouvier, J.-M. Fournier,and P. Senn “A 27-MHz Digital-to-analog Video Processor,”  IEEE J. solid-state circuits, vol. 23, no. 6,  pp.1358-1369, Dec.1998. [8]    N. Ghittori, A. Vigna, P. Malcovati, S.D’Amico, A. Baschirotto, “1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS,WLAN/Bluetooth) Transmitters,”  IEEE J. solid-state circuits, vol. 41, no. 9, pp.1970-1982, Sept.2006. [9]   S. Luschas, R. Schreier, H.-S. Lee, “Radio Frequency Digital-to-Analog Converter,”  IEEE J. solid-state circuits, vol. 39, no. 9, pp.1462-1467, Sept. 2004.
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