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fm28v020_datasheet.pdf

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FM28V020 256-Kbit (32 K × 8) F-RAM Memory 256-Kbit (32 K × 8) F-RAM Memory Features ■ Packages:
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  FM28V020 256-Kbit (32 K × 8) F-RAM Memory CypressSemiconductorCorporation ã198 Champion CourtãSanJose , CA95134-1709ã408-943-2600Document Number: 001-86204 Rev. *F Revised August 12, 2015 256-Kbit (32 K ×8) F-RAMMemory Features ■ 256-Kbit ferroelectric random access memory (F-RAM)logically organized as 32 K × 8 ❐ High-endurance 100 trillion (10 14 ) read/writes ❐ 151-year data retention (see the Data Retention andEndurance table) ❐ NoDelay™ writes ❐ Page mode operation ❐  Advanced high-reliability ferroelectric process ■ SRAM compatible ❐ Industry-standard 32 K × 8 SRAM pinout ❐ 70-ns access time, 140-ns cycle time ■ Superior to battery-backed SRAM modules ❐ No battery concerns ❐ Monolithic reliability ❐ True surface mount solution, no rework steps ❐ Superior for moisture, shock, and vibration ❐ Resistant to negative voltage undershoots ■ Low power consumption ❐  Active current 5 mA (typ) ❐ Standby current 90   A (typ) ■ Low-voltage operation: V DD  = 2.0 V to 3.6 V ■ Industrial temperature: –40  C to +85  C ■ Packages: ❐ 28-pin small outline integrated circuit (SOIC) package ❐ 28-pin thin small outline package (TSOP) Type I ❐ 32-pin thin small outline package (TSOP) Type I ■ Restriction of hazardous substances (RoHS) compliant Functional Overview The FM28V020 is a 32 K × 8 nonvolatile memory that reads andwrites similar to a standard SRAM. A ferroelectric randomaccess memory or F-RAM is nonvolatile, which means that datais retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns,functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and highwrite endurance make the F-RAM superior to other types of memory. The FM28V020 operation is similar to that of other RAM devicesand therefore, it can be used as a drop-in replacement for astandard SRAM in a system. Read and write cycles may betriggered by CE or simply by changing the address. The F-RAMmemory is nonvolatile due to its unique ferroelectric memoryprocess. These features make the FM28V020 ideal for nonvolatile memory applications requiring frequent or rapidwrites. The device is available in a 28-pin SOIC, 28-pin TSOP I and32-pin TSOP I surface mount packages. Device specificationsare guaranteed over the industrial temperature range –40 °C to+85 °C.For a complete list of related documentation, click here.    A   d   d  r  e  s  s   L  a   t  c   h CEControl LogicWE    R  o  w    D  e  c  o   d  e  r  AI/O Latch & Bus Driver OEDQ32 K x 8F-RAM Array  . . . Column Decoder  . . . 14-3 A2-07-0 A14-0 Logic Block Diagram  FM28V020 Document Number: 001-86204 Rev. *F Page 2 of 21 Contents Pinouts ..............................................................................3Pin Definitions ..................................................................4Device Operation ..............................................................5 Memory Operation .......................................................5Read Operation ...........................................................5Write Operation ...........................................................5Page Mode Operation .................................................5Pre-charge Operation ..................................................5SRAM Drop-In Replacement .......................................6Endurance ...................................................................6 Maximum Ratings .............................................................7Operating Range ...............................................................7DC Electrical Characteristics ..........................................7Data Retention and Endurance .......................................7Capacitance ......................................................................8Thermal Resistance ..........................................................8 AC Test Conditions ..........................................................8 AC Switching Characteristics .........................................9 SRAM Read Cycle ......................................................9SRAM Write Cycle .....................................................10 Power Cycle Timing .......................................................13Functional Truth Table ...................................................14Ordering Information ......................................................15 Ordering Code Definitions .........................................15 Package Diagrams ..........................................................16 Acronyms ........................................................................19Document Conventions .................................................19 Units of Measure .......................................................19 Document History Page .................................................20Sales, Solutions, and Legal Information ......................21 Worldwide Sales and Design Support .......................21Products ....................................................................21PSoC® Solutions ......................................................21Cypress Developer Community .................................21Technical Support .....................................................21  FM28V020 Document Number: 001-86204 Rev. *F Page 3 of 21 Pinouts Figure 1. 28-pin SOIC pinoutFigure 2. 28-pin TSOP I pinoutFigure 3. 32-pin TSOP I pinout DQ 4 DQ 5 DQ 6 DQ 7 OE A 8  A 13 WE A 9  A 10  A 11 V DD CEDQ 3  A 14  A 3  A 2  A 1  A 0 DQ 0 DQ 1 DQ 2 V SS  A 12  A 7  A 6  A 5  A 4 28-pin SOIC(x 8)Top view(not to scale) 12341314567891011121615191817212024232226252827 A 0 DQ 0 DQ 1 DQ 2 DQ 7  A 10 CEDQ 6 DQ 3 DQ 5  A 1 WEV DD  A 14  A 12  A 7  A 6  A 5  A 4 OE A 11  A 9  A 8  A 13 28-pin TSOP I(x 8)Top view(not to scale) 22232456252627281234109131211151418171620192178 A 3  A 2 V SS DQ 4  A 0 DQ 0 DQ 1 DQ 2 DQ 7  A 10 CEDQ 6 DQ 3 DQ 5 NC A 1 NCWEV DD  A 14  A 12  A 7  A 6  A 5  A 4 OE A 11  A 9  A 8  A 13 32-pin TSOP I(x 8)Top view(not to scale) 1234131456789101112201923222125242827263029323115161817 A 3 NC A 2 NCV SS DQ 4  FM28V020 Document Number: 001-86204 Rev. *F Page 4 of 21 Pin Definitions Pin NameI/O TypeDescription  A 14  –A 0 Input  Address inputs : The 15 address lines select one of 32,768 bytes in the F-RAM array. The lowest twoaddress lines A 2  –A 0  may be used for page mode read and write operations.DQ 7  –DQ 0 Input/Output Data I/O Lines : 8-bit bidirectional data bus for accessing the F-RAM array.WEInput Write Enable : A write cycle begins when WE is asserted. The rising edge causes the FM28V020 to writethe data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for page mode write cycles. CEInput Chip Enable : The device is selected and a new memory access begins on the falling edge of CE. Theentire address is latched internally at this point. Subsequent changes to the A 2  –A 0 address inputs allowpage mode operation. OEInput Output Enable : When OE is LOW, the FM28V020 drives the data bus when the valid read data isavailable. Deasserting OE HIGH tristates the DQ pins.V SS GroundGround for the device. Must be connected to the ground of the system.V DD Power supplyPower supply input to the device. NCNo connectNo connect. This pin is not connected to the die.
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