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Generic IC EMC Test Specification

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    Generic IC EMC Test Specification      IMPRESSUM Title: Generic IC EMC Test Specification  © ZVEI copyright 2010 Published by: ZVEI - Zentralverband Elektrotechnik und Elektronikindustrie e.V. (ZVEI – German Electrical and Electronic Manufactures' Association) Electronic Components and Systems Devision Lyoner Straße 9 60528 Frankfurt am Main Fon 069 6302-465 Fax 069 6302-407 Mail zvei-be@zvei.org www.zvei.org Contact in the ZVEI: Dr. Rolf Winter  Authors: Joester, Michael Continental Automotive GmbH Klotz, Dr. Frank Infineon Technologies AG Pfaff, Dr. Wolfgang Robert BOSCH GmbH Steinecke, Thomas Infineon Technologies AG Photo (Cover):  Adam Opel GmbH Infineon Technologies AG This document may be reproduced according to the copyright and liability chapter free of charge in any format or medium providing it is reproduced accurately and not used in a misleading context. The material must be acknowledged as ZVEI copyright and the title of the document has to be specified. A complimentary copy of the document where ZVEI material is quoted has to be provided. Every effort was made to ensure that the information given herein is accurate, but no legal responsibility is accepted for any errors, omissions or misleading statements in this information. The Document and supporting materials can be found on the ZVEI website at: www.zvei.org/ecs under the rubric Publikationen Revision: January 2010 Based on BISS Version 1.2 of November 2007  TABLE OF CONTENT TABLE OF CONTENT 1. Scope ....................................................................................................................................... 6   2. General and objective ............................................................................................................... 6   3. Normative reference ................................................................................................................. 7   4. Definitions ................................................................................................................................ 8   5. Splitting ICs into IC function modules ...................................................................................... 13   5.1 Matrix for splitting ICs ......................................................................................................... 13   5.2 Example of an IC built up with IC function modules ............................................................. 14   6. Test definitions ....................................................................................................................... 15   6.1 Test methods ..................................................................................................................... 15   6.2 Test parameters ................................................................................................................. 15   6.3 DUT Monitoring .................................................................................................................. 17   7. Test and measurement selection guide ................................................................................... 18   7.1 Workflow for selection and test ........................................................................................... 18   7.1.1 Conducted tests ............................................................................................................ 19   7.1.2 Identification of IC function modules .............................................................................. 19   7.1.3 Pin Selection for Emission and Immunity ........................................................................ 19   7.1.4 IC function module and the coupling or injection points .................................................. 20   7.1.5 Selection guide emission ............................................................................................... 20   7.1.6 Selection guide immunity ............................................................................................... 21   7.2 Radiated tests .................................................................................................................... 22   7.2.1 Criteria for performing radiated Emission and Immunity Tests ........................................ 22   7.2.2 Selection guide emission ............................................................................................... 22   7.2.3 Selection guide immunity ............................................................................................... 22   8. Test and measurement networks ............................................................................................. 23   8.1 Port module ........................................................................................................................ 24   8.1.1 Line Driver .................................................................................................................... 24   8.1.2 Line Receiver ................................................................................................................ 25   8.1.3 Symmetrical Line Driver ................................................................................................. 26   8.1.4 Symmetrical Line Receiver ............................................................................................ 27   8.1.5 Regional Driver ............................................................................................................. 28   8.1.6 Regional Input ............................................................................................................... 29   8.1.7 High Side driver ............................................................................................................ 30   8.1.8 Low Side driver ............................................................................................................. 32   8.2 Supply module ................................................................................................................... 34   8.3 Core module ....................................................................................................................... 35   8.4 Oscillator module ............................................................................................................... 35   8.5 Signal decoupling- and monitoring setup ............................................................................. 36   8.6 Entire IC ............................................................................................................................. 38   9. Functional Configurations and Operating Modes ..................................................................... 39   9.1 Emission test configuration for ICs without CPU .................................................................. 39   9.2 Immunity test configuration for ICs without CPU .................................................................. 41   9.3 Emission test configuration for ICs with CPU ...................................................................... 44   9.3.1 Test initialization software module for cores containing a CPU ....................................... 44   9.3.2 Immunity test configuration for ICs with CPU ................................................................. 47   9.3.3 Test loop software module for cores containing a CPU ................................................... 48   10. Test board ............................................................................................................................ 49  Introduction Normative References Definitions Test and Measurement Selection Guide Test and Measurement Networks Functional Configurations and Operating Modes Test Board  TABLE OF CONTENT 4 11. “Preliminary” IC EMC limits for Automotive ............................................................................ 50   11.1 Emission .......................................................................................................................... 50   11.1.1 Emission level scheme ................................................................................................ 50   11.1.2 General emission limit classes ..................................................................................... 51   11.1.3 Dedicated emission limits for 'external digital bus systems' .......................................... 53   11.2 Immunity .......................................................................................................................... 54   11.2.1 General immunity limit classes ..................................................................................... 54   12. IC EMC Specification ............................................................................................................ 55   13. Test report ............................................................................................................................ 57   14. Copyrights and Liability ......................................................................................................... 58   15. Contacts and authors ............................................................................................................ 59    Annex A Layout Recommendation, (informative) ......................................................................... 60   Layout Example of 150 Ω  networks on 2 layer and multi layer PCB ............................................. 60   Layout Example of 1 Ω  network on 2 layer and multi layer PCB .................................................. 60   Layout Example of DPI network on 2 layer and multi layer PCB ................................................... 61   Layout Example of a TEM cell test board .................................................................................... 62   Layout Example for Digital systems built with IC types microcontrollers, RAMs  ............................ 63    Annex B Test network modification (emission, normative) ........................................................... 69    Annex C Trace impedance calculation (informative) .................................................................... 71    Annex D Modulation definition (immunity, informative) ................................................................. 73    Annex E Example of an IC EMC specification (general, informative) ............................................ 74    Annex F Calculation of pin specific limits (general, informative) ................................................... 76   IC EMC Test Limits Testing Documents Terms of Usage Annexes
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