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HNC - Analogue/Digital - Assign 2 - Op Amps

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HNC Electrical & Electronic Engineering Analogue & Digital Devices Assignment 2 - Operational Amplifiers Teesside University, delivered by Middlesbrough College
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    Operational Amplifiers HNC Electrical and Electronic Engineering Year One - 2013/14 Module: Digital & Analogue Devices Keith A. Hudson   M1306117 11/03/2014   <This page is intentionally blank>  Keith A. Hudson 2 Digital & Analogue Devices M1306117 05 March, 2014 HNC Electrical and Electronic Engineering Year One: 2013/14 Contents 1   Assumptions ............................................................................................................................................... 6   2   Adder / Subtractor Circuit (Task 1a) ........................................................................................................... 7   2.1   Requirements ...................................................................................................................................... 7   2.2   Circuit Simulation Using Proteus ......................................................................................................... 8   2.3   Actual Circuit ..................................................................................................................................... 15   3   Integration Circuit (Task 1b) ..................................................................................................................... 17   3.1   Requirements .................................................................................................................................... 17   3.2   Circuit Simulation Using Proteus ....................................................................................................... 18   3.3   Actual Circuit ..................................................................................................................................... 21   4   4-bit Analogue to Digital Convertor Circuit (Task 1c) ............................................................................... 23   4.1   Requirements .................................................................................................................................... 23   4.2   Circuit Simulation Using Proteus ....................................................................................................... 25   4.3   Actual Circuit ..................................................................................................................................... 34   5   Conclusions ............................................................................................................................................... 36   6   Bibliography .............................................................................................................................................. 37    Keith A. Hudson 3 Digital & Analogue Devices M1306117 05 March, 2014 HNC Electrical and Electronic Engineering Year One: 2013/14 Figures Figure 1: Adder / Subtractor circuit ................................................................................................................... 8   Figure 2: Testing i/p A ........................................................................................................................................ 9   Figure 3: Testing i/p B ...................................................................................................................................... 10   Figure 4: Testing i/p C ...................................................................................................................................... 11   Figure 5: A = 5 V, B = 4 V, Output = 1.3 V......................................................................................................... 12   Figure 6: A = 5 V, B = 4 V, C = 2 V, Output = 0.3 V ........................................................................................... 13   Figure 7: A = 5 V, B = 4 V, C = 5 V, Output = -1.2 V .......................................................................................... 14   Figure 8: Adder / subtractor circuit ................................................................................................................. 15   Figure 9: Multi-meters showing the actual output from each Op Amp .......................................................... 16   Figure 10: Op Amp Integrator circuit ............................................................................................................... 17   Figure 11: The simulated Integrator Circuit ..................................................................................................... 18   Figure 12: The input and output wave forms .................................................................................................. 19   Figure 13: Input / Output ranges ..................................................................................................................... 19   Figure 14: Output voltage at 0.4s .................................................................................................................... 20   Figure 15: integrator circuit on breadboard .................................................................................................... 21   Figure 16: Power supply................................................................................................................................... 21   Figure 17: Function generator producing the square wave input for the integrator ..................................... 21   Figure 18: Setting up the PSU and initial oscilloscope output ......................................................................... 22   Figure 19: Oscilloscope output ........................................................................................................................ 22   Figure 20: Input 0000, Output 0 ...................................................................................................................... 25   Figure 21: Input 0001, Output 1 ...................................................................................................................... 26   Figure 22: Input 0010, Output 2 ...................................................................................................................... 26   Figure 23: Input 0011, Output 3 ...................................................................................................................... 27   Figure 24: Input 0100, Output 4 ...................................................................................................................... 27   Figure 25: Input 0101, Output 5 ...................................................................................................................... 28   Figure 26: Input 0110, Output 6 ...................................................................................................................... 28   Figure 27: Input 0111, Output 7 ...................................................................................................................... 29   Figure 28: Input 1000, Output 8 ...................................................................................................................... 29   Figure 29: Input 1001, Output 9 ...................................................................................................................... 30   Figure 30: Input 1010, Output 10 .................................................................................................................... 30   Figure 31: Input 1011, Output 11 .................................................................................................................... 31  
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