Human nervous system function emulator

Human nervous system function emulator
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  Human Nervous System Function Emulator Paul Frenger MD A Working Hypothesis, Inc. P.O. Box 820506 Houston, TX 77282-0506 USA ABSTRACT This paper describes a modular, extensible, open-systems design for a multiprocessor network which emulates the major functions of the human nervous system. Interchangeable hardware/software components, a socketed software bus with plug-and-play capability and self diagnostics are included. The computer hardware is based on IEEE P996.1 bus cards. Its operating system utilizes IEEE 1275 standard software. Object oriented design techniques and programming are featured. A machine-independent high level script-based command language was created for this project. Neural anatomical structures which were emulated include the cortex, brainstem, cerebellum, spinal cord, autonomic and  peripheral nervous systems. Motor, sensory, autoregulatory, and higher cognitive artificial intelligence, behavioral and emotional functions are provided. The author discusses how he has interfaced this emulator to machine vision, speech recognition/speech synthesis, an artificial neural network and a dexterous hand to form an android robotic platform. KEYWORDS robotics, artificial intelligence, artificial neural network, IEEE P996.1 bus IEEE 1275 software, Forth language, object oriented programming, software emulator 1. INTRODUCTION: EMULATING BRAIN FUNCTION  Neurophysiology and brain function has been a passion of mine since I attended medical school in the early 1970's. A quarter of a century later, much more is known of nervous system functioning and the effects of various lesions and disease states. Further, computer technology has advanced dramatically in the last decade, enabling a very realistic human nervous system functional emulator to be created. This project has undergone major hardware and software revisions recently, as described below. This work product has been Grafted as an open systems design, that is, one which can be easily shared among like-minded investigators. I do not believe that it is necessary to slavishly depict every brain structure and nerve pathway in order to adequately reproduce the totality of nervous system function. This design reflects that belief. However, those who wish to extend this plan with increasing levels of operational detail are encouraged to do so, in the hope that this will facilitate important new discoveries. Some researchers [I], myself included, strongly believe that for an artificial "mind" to function properly, to approach a conscious state, it must have some kind of a "body" to give it a sense of self  . The process of providing a lifelike humanoid body for this artificial brain/mind is discussed below. 289 Presented at: Rocky Mountain Bioengineering Symposium, 2000, USAF Academy CO, pg.289-294  2. MATERIALS AND METHODS In 1995 I created a multiprocessor control network to form the foundation of this human nervous system function emulator [2]. It consisted of a 10 MHz NEC V-25 single board computer (SBC) serving as the cortex/brainstem/cerebellum and five 8 MHz Motorola 68HC11 SBCs acting as spinal cord and extremity controllers. Serial communications over this network was bidirectional at 1 Mbits/second, with efferent motor signals and afferent sensory data. High level communications were accomplished with a custom machine-independent high level script-based command language, which I called  Android.Forth  [3]. Low level communications were accomplished by converting these ASCII scripts into bit-encoded command streams. An example script might be: CURL RIGHT INDEX FINGER This script could be part of a complex routine to make a fist. The script was generated in the V-25 SBC where it was translated, expanded and encoded. The low level encoded bit streams generated as a result would be sent over the high-speed serial network to the right extremity SBC, fully flex the distal interphalangeal joint (DIP), the proximal interphalangeal joint (PIP), and the metacarpophalangeal joint (MCP) of the right hand, second digit. One philosophy behind this project was to create hardware/software modular components with simple interfacing requirements. This approach enables a module's function to be emulated in software or achieved with specialized hardware on a plug-in substitution basis. An example of this principle familiar to programmers is the provision of a C compiler option for software floating point emulation when a hardware floating point processing unit is not available. An example taken from this design is the use of an analog artificial neural network   (ANN) coprocessor [4] for optical character recognition (OCR). The analog board achieves the equivalent of 160 MFlops processing power using eight LM324 quad operational amplifiers (op-amps). Input to this board comes from a CMOS camera's  frame grabber  ; the output from the board is a stream of ASCII characters. Before the coprocessor board was added, OCR functions were emulated in software on the main single board computer. In both cases the input from the camera's frame grabber and the final ASCII output were just the same, giving a "socketed" functional equivalency between these two techniques. An analog "emotion chip" based on the Dallas Semiconductor DS1667 dual op-amp with dual digital  potentiometer integrated circuit (IC) was also added [5]. It replaced a previous (equivalent) software simulation run on the main SBC. Like the ANN above, it too was connected in a "socketed" fashion. Another example: speech recognition/speech synthesis functions have been provided by two different systems. A simple speech recognition board based on the Hualon Microelectronics HM2007 chip [6] is coupled with a Votrax SC-01 CMOS speech synthesizer chip to form a limited capacity portable voice I/O unit. A much more capable voice I/O unit based on Bell Labs speech recognition/synthesis software [7] running on the Pentium/Sound Blaster system described below was later substituted for the simpler one. In either case the input to the speech recognition board was a microphone and the output was an ASCII stream; and the input to the speech synthesizer was ASCII text, the output being spoken English. More computational power was eventually required of this network as additional functions were added. The old multiprocessor control system was dismantled and all of its functions were moved into a 200 290  MHz Intel Pentium MMX desktop PC which had both ISA and PCI expansion slots. The previous external SBC-to-SBC serial communications arrangement became unnecessary, so changes were made to  Android.Forth  to accommodate the new hardware environment. A desktop PC form factor is too large to be suitable for placement within an android robot body. So as to miniaturize and standardize the computer hardware, the current version of this system employs  IEEE P996.1  (PC/104) bus cards. A standard PC/104 card is 3.550 inches by 3.775 inches and is stackable, 0.600 inches apart. IEEE P996.1 is based on the IBM PC/AT (ISA) bus. The cards used are: a  frame grabber   for machine vision; a Sound Blaster   for speech recog-nition/ synthesis; a multi-I/0 card   for interfacing body sensors and actuators; and  prototyping cards  for the analog ANN and emotion chip coprocessor parts. Figure 1 depicts the new hardware arrangement; the old multiprocessor network is outlined on the front of the CPU card which replaces it (the network will likely be revived soon by replacing the 68HC11 SBCs with Dallas Semiconductor DS80C390 120 MHz Intel 8051 "workalikes"). 3. CORE SOFTWARE: IEEE 1275 AND A MULTITASKING FORTH The key to the design and programming of this emulator as an open system  is the use of the  IEEE 1275 standard [8] for boot firmware (also known as "open firmware", and herein referred to as OF). OF was designed to be a CPU-and-bus-independent firmware platform for performing all necessary "boot" or startup operations for computer workstations prior to loading of the host operating system and user  programs. OF has been adopted by Sun Microsystems for its Solaris  workstations and for its Java/OS;  by Apple computer for the  Mac/OS  ; and by IBM for its PCs, among others. OF is based on the Forth  programming language as defined in ANSI X3.215-1994 [9]. Forth is unusually well-suited to real-time embedded control systems, including robotics [10]. 291  OF exhibits many object oriented programming  (OOP) features. For example, hardware and software are encapsulated in an object   called a device node . A device node can be a plug-in card, a bus portal or other entity. Collections of device nodes are organized into a hierarchical tree structure called a device tree . The nodes contain  packages , which represent the name, properties, methods (i.e.: device drivers) and private data of each node. A package can inherit general-purpose methods and access public data from its  parent class . Forth "tricks" can be used to make OF programs resemble C++ more closely [11]. Programs are stored as a bytecoded, 12-bit tokenized representation of Forth source called FCode . Downloading FCode is much faster than downloading ASCII source code. OF development systems include an FCode   tokenizer   which converts Forth source code into FCode tokens, and an FCode interpreter   program to execute these tokens at runtime. When system power is applied, the main CPU executes OF. OF performs a self test, initializes board- level resources and then begins "probing" for plug-in devices. OF initializes these components and adds their identification information to the device tree database. This creates a  plug-and-play  type system. In a typical workstation computer, after the add-on components have been started up, OF loads the native operating system (OS) from mass storage and then "goes away", turning the system over to the OS. But OF doesn't have to go away, it can stay resident and itself serve as an ANSI Forth-based OS. OF is available commercially [12], but it can be implemented as an add-on to an appropriate Forth language interpreter/compiler. My version of OF is modeled after Firmware Factory , a public domain IEEE 1275 variant intended for 8-bit and 16-bit embedded processor applications [13]. This emulator project is programmed in  Modular Forth v3.6   for the Intel 80x86, supplied by Microprocessor Engineering of Southampton, England [14]. Modular Forth supports separately compiled code modules (in Forth, C, Pascal, assembler, etc.); extensive utilities and online help manuals; and multitasking both by pre-emptive time-slicing and cooperative round-robin techniques. Modular Forth is an MS/DOS 16-bit Forth-83 standard product which has a 32-bit Windows upgrade  path available; its code is stable after years of commercial use; and it is very inexpensive. For those software modules requiring a tree-indexing capability for keyword retrieval, I use  Btrieve v6.15  by Pervasive Software [15]. Modular Forth comes with a Btrieve interface. 4. SOME NEURAL EMULATOR FUNCTIONAL DETAILS When the multiprocessor network was in operation, SBCs representing various brain structures shuttled data from board to board over the serial lines. The new emulator employs multitasking modules  in the solitary CPU SBC instead. For example, afferent sensory data enters the system at a port; a task representing the dorsal root of the spinal cord filters this input and stores it in a RAM buffer. Another task representing the spinoreticular/spinothalamic tracts reads this buffer, further processes the data (tagging it with input type, location and intensity) and moves it to a brainstem buffer area. Still other tasks will examine, transform and move this data to buffers representing the thalamus and sensory cortex areas. This general approach to nervous system function is employed throughout the emulator. Short term memory  in this brain uses temporary RAM buffering.  Long term memory  is kept on disk. An indexed, permanent entry for each known word is stored in a data structure which contains the name of the word, its pronunciation, its part of speech, at least one definition, a picture if applicable, its emotional valence and pointers to extended data, if any (ie: synonyms, antonyms, additional definitions). 292   Higher cortical (intellectual) functions are based on a much-modified schema mechanism  proposed by Drescher [16]. A schema is a conceptual data structure which resembles an OOP object. It contains  private data ("items", "contexts", "results") and methods ("actions"). Items represent the state of objects in the surrounding world. Actions are high level scripts. Results are measurable outcomes of actions. A schema may be extended by combining scripts, contexts and results with other schemas to form a more complex concept or plan of action. Schemas are refined by a learning process which reinforces effective actions and inhibits ineffective ones. The generated scripts can be contemplated   (without taking action), executed   (performing the indicated actions) or saved   (as part of the learning process). A consciousness routine in the main SBC controls the sleep/waking cycle of this nervous system function emulator. While awake, the sensory buffers, schema heap and scratchpad areas in RAM slowly fill up with data. This eventually overwhelms the garbage collection task   (which runs continuously in the background) and somnolence becomes irresistible. During sleep, consciousness and motor functions are disabled, dreaming is enabled and the garbage collection process predominates. After awhile, all sensory data and concept scratchpad areas are processed, transferred to mass storage and the RAM  buffers released. The sleeper soon awakens and consciousness resumes.  Notably, there is a software task which represents the functions of the prefrontal cortex. This area monitors internal and external states and initiates appropriate actions. For example, decreased battery voltage is interpreted as "hunger"; this condition increases anxiety levels, eventually triggering a search for replacement energy. Internal clocks monitor voluntary activities (such as reading) and can produce a condition of boredom and sleepiness. A list of favorite activities is held in memory and any of these can initiate actions (ie: requesting a car ride or listening to music) when a threshold function is exceeded. 5. THE FIRST EMULATOR APPLICATION: "ANNIE" THE ANDROID ROBOT The above-mentioned emulator has been partially integrated into an android robot which I call "ANNIE", which is an acronym for "artificial neural network (with) innate emotions". ANNIE resembles a three year old human female, thirty-six inches tall. She has color vision, a dexterous right hand/arm, speech recognition/speech synthesis and facial expressiveness. ANNIE is a work in progress, so she is presently wheelchair-bound. This wheelchair platform facilitates some currently necessary sleight-of-hand in the form of an extracorporeal power supply and auxiliary computer chassis. Her artificial brain uses the computer hardware, CNS simulations, analog ANN and emotion chip described above. Her mind-model includes: intellect, memory, ego, personality, gender and emotions. She has various likes and dislikes. Her belief system and self awareness have been programmed to  produce the illusion that she is alive. She has the ability to learn, and exhibits the quality of curiosity. ANNIE'S intellect can be upgraded with faster CPU boards, additional RAM and mass storage. 293
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