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  Efficient canonic signed digit recoding Gustavo A. Ruiz n , Mercedes Granda Departamento de Electro´nica and Computadores, Facultad de Ciencias, Avda. de Los Castros s/n, Universidad de Cantabria, 39005 Santander, Spain a r t i c l e i n f o  Article history: Received 14 December 2010Received in revised form14 June 2011Accepted 17 June 2011Available online 6 July 2011 Keywords: Canonic signed digit (CSD)Digital arithmeticMinimal signed digitSigned digit representation a b s t r a c t In this work novel-efficient implementations to convert a two’s complement binary number into itscanonic signed digit (CSD) representation are presented. In these CSD recoding circuits two signals,  H  and  K  , functionally equivalent to two carries are described. They are computed in parallel reducing thecritical path and they possess some properties that lead to a simplification of the algebraic expressionsminimizing the overall hardware implementation. As a result, the proposed circuits are highly efficientin terms of speed and area in comparison with other counterpart previous architectures. Simulations of different configurations made over standard-cell implementations show an average reduction of about55% in the delay and 29% in the area for a ripple-carry scheme, 47% in the delay and 17% the area in acarry look-ahead scheme, and 36% in the delay and 31% the area in a parallel prefix scheme. &  2011 Elsevier Ltd. All rights reserved. 1. Introduction The canonical signed digit (CSD) representation is one of theexisting signed digit (SD) representations with unique featureswhich make it useful in certain DSP applications focusing on low-power, efficient-area and high-speed arithmetic [1]. The CSD codeis a ternary number system with the digit set {1¯  0 1}, where 1¯ stands for 1. Given a constant, the corresponding CSD representa-tion is unique and has two main properties: (1) the number of nonzero digits is minimal, and (2) no two consecutive digits areboth nonzero, that is, two nonzero digits are not adjacent. Thefirst property implies a minimal Hamming weight, which leads toa reduction in the number of additions in arithmetic operations.The second property provides its uniqueness characteristic. How-ever, if this property is relaxed, this representation is called theminimal signed digit (MSD) representation, which has as manynonzeros as the CSD representation, but which provides multiplerepresentations for a constant [2,3]. CSD representation has proven to be useful for the design andimplementation of digital filters such as the area-efficient program-mable FIR digital filter architecture in Ref. [4], Chebyshev FIR filter design with some constrains in terms of hardware and frequencydomain in Ref. [5], low-complexity algorithms for design filters inRef. [6], 2D FIR and IIR filter design in Ref. [7] and the digit-serial CSD filter FPGA architecture for image conversion proposed inRef. [8]. It has also been used in the reduction of the complexityof digital filters [9–11] or matrix multipliers [12] applying shared subexpression methods. CSD code has been largely exploited toimplement efficient multipliers [13–15]. It enables the reduction of  the number of partial products that must be calculated fast, andalso low-power consumption and low area structure of a multiplierfor DSP applications [16] or self-timed circuits [17]. In fixed-width multipliers, CSD succeeded in reducing the mean square error [18]or the compensation error using efficient sign extension [19].Finally, other applications of CSD coding in reversible image colortransforms [20], Montgomery exponentiation [21,22] or vector rotational CORDIC [23] have been proposed.Many researchers have addressed the question of CSD recodingto convert two’s complement into CSD code. Already in 1960,Reitwiesner proposed an algorithm for converting two’s comple-ment numbers to a minimum weight radix-2 (binary) signed digitrepresentation [24]. From the practical point of view, the traditionalapproach to generate the CSD representation uses look-up table[25,26]. Here, there is a great similarity in the carry definition used in CSD recoding and in conventional adders, which suggest that theimplementation of fast CSD converters should be based on well-known structures of classical adders. However, some algorithms toconvert two’s complement into CSD numbers try to reduce thecomputational complexity [27,28], but are not suitable for hard- ware implementation. Other hardware approaches propose the by-pass method [29], fast carry look-ahead circuits [30] or parallel prefix schemes [31,32] to reduce hardware but they only focus on carry optimization without considering the overall CSD recoding.All of these algorithms generate the CSD code recursively from theleast significant bit (LSB) to the most significant bit (MSB). How-ever, in some applications, such as the computation of exponentia-tion, the conversion from MSB to LSB brings some advantages. Contents lists available at ScienceDirectjournal homepage: www.elsevier.com/locate/mejo Microelectronics Journal 0026-2692/$-see front matter  &  2011 Elsevier Ltd. All rights reserved.doi:10.1016/j.mejo.2011.06.006 n Corresponding author. E-mail addresses:  ruizrg@unican.es (G.A. Ruiz),grandam@unican.es (M. Granda).Microelectronics Journal 42 (2011) 1090–1097  Okeya et al. [33] proposed an algorithm to carry out this conversionbut it requires additional memory to store some precomputedelements. Indeed, efficient MSB-to-LSB algorithms yield a MSDrepresentation [34,35] but not a CSD one because of having consecutive nonzero digits.This paper presents novel, efficient standard cell-based imple-mentations to convert a two’s complement binary number into itsCSD representation based on two signals,  H   and  K  , functionallyequivalent to two carries. These signals were already defined inthe implementation of 3X terms for radix-8 encoding [36], buthere they are used for the CSD recoding in a more resourcefulway. Implementations in a 130 nm standard cell CMOS technol-ogy of previously published architectures have been comparedwith the proposed scheme demonstrating that the circuits arehighly efficient in area and speed. The remainder of this paper isorganized as follows. In Section 2, a brief introduction anddefinitions related to CSD recoding are presented. New compactalgebraic expressions for optimal CSD recoding in terms of signals  H   and  K   and their application in the efficient implementation of CSD recoders for different configurations are described in Section3. Simulations and comparisons are listed in Section 4. Finally, theconclusions are stated in Section 5. 2. CSD recoding  The CSD representation of an integer number is a signed andunique digit representation that contains no adjacent nonzerodigits. Given an  n -digit binary unsigned number  X  ¼ {  x 0 ,  x 1 ,  y ,  x n  1 } expressed as  X   ¼ X n  1 i  ¼  0  x i U 2 i ,  x i A f 0 , 1 g ð 1 Þ then the ( n þ 1)-digit CSD representation  Y  ¼ {  y 0 ,  y 1 , y ,  y n } of   X   isgiven by Y   ¼ X n  1 i  ¼  0  x i U 2 i ¼ X ni  ¼  0  y i U 2 i ,  y i A f 1 , 0 , 1 g ð 2 Þ The condition that all nonzero digits in a CSD number areseparated by zeros implies that  y i þ 1 U  y i  ¼ 0 ,  0 r i r n  1  ð 3 Þ From this property, the probability that a CSD  n -digit has anonzero value [13,26] is given by P  ð 9  y i 9  ¼ 1 Þ ¼  13  þ  19 n  1   12   n    ð 4 Þ As  n  becomes large, this probability tends to 1/3 while thisprobability becomes 1/2 in a binary code. Using this property, thenumber of additions/subtractions is reduced to a minimum inmultipliers [14–17] and, as a result, an overall speed-up can be achieved.The adoption of a ternary number system adds some flexibilityto the CSD representation, since it allows the number of nonzerodigits to be minimized, but it requires that each digit  y i  must beencoded over two bits {  y si ,  y di  }. Table 1 shows the two mostfrequently used encodings in practice [1]. Encoding 1 can beviewed as a two’s representation. However, encoding 2 is prefer-able since it satisfies the following relation  y i  ¼  y di    y si  ð 5 Þ where  y si  represents the sign bit and  y di  the data bit. This encodingalso allows an additional valid representation of 0 when  y si  ¼ 1 and  y di  ¼ 1, which is useful in some arithmetic implementations. In thewhole paper, this encoding is used.Hashemian [27] presented the binary coded CSD (BCSD)number to avoid extra data word representation. The BCSDrecoding is based on a simple binary representation  B ¼ { b 0 , b 1 , y , b n  1 } of a CSD code, which uses the same number of bitsas the srcinal two’s complement representation. It takes advan-tage of the CSD property, in which no two adjacent digits can bothbe nonzero, to assign the next position of each nonzero CSD digitas sign bit while maintaining the same size data word. Thus, if thebit  i  in a CSD code is nonzero,  y i a 0 (which means that  y i þ 1 ¼ 0),then the bit  i  is nonzero in the BCSD code,  b i a 0, and thefollowing bit  b i þ 1  acts as a sign bit:  b i þ 1 ¼ 0 means  y i  is positiveand  b i þ 1 ¼ 1 means  y i  is negative. As a result,  y i ¼ 0 is encoded as b i ¼ 0,  y i ¼ 1 as  b i þ 1 b i ¼ 01 and  y i ¼ 1¯  as  b i þ 1 b i ¼ 11. A simpleconversion between a CSD coding and BCSD coding is b i  ¼  y di  þ  y si  1 b i þ 1  ¼  y di þ 1  þ  y si  ð 6 Þ Since this conversion can be obtained by a simple operation, inthis paper the two-bit encoding representation is used to make itsreading and understanding easier, and, without loss of generality,it can be straightforwardly extended to other representations.The conversion from a binary representation to CSD represen-tation is mostly based on the following identity2 i þ  j  1 þ 2 i þ  j  2 þ . . . þ 2 i ¼ 2 i þ  j  2 i ð 7 Þ This means that a string of 1s can be replaced by a 1, followedby 0s, followed by a 1¯ . Isolated 1s are left unchanged, but isolated0s are re-examined in such a way that, after applying Eq. (7), pairsof type 11¯  are changed to 01. For example, the binary number(001010111) 2  is equivalent in a CSD representation to 0101¯ 01¯ 001¯ ;the encoding process is graphically shown in Fig. 1. Traditionally,this encoding is performed from LSB to MSB using two adjacentbits and a carry signal according to the recoding algorithm shownin Table 2 [25,26]. Here, the carry-out  c  i ¼ 1 if and only if there aretwo of three 1s among the three inputs  x i þ 1 ,  x i  and  c  i  1 , that is c  i  ¼  x i  x i þ 1  þð  x i  þ  x i þ 1 Þ c  i  1 ,  being  c   1  ¼ 0  ð 8 Þ The variable  D ¼ { d 0 ,  d 1 , y , d n  1 }, which flags all nonzero digitsin the CSD representation, is defined as d i  ¼  x i    c  i  1  ð 9 Þ  Table 1 Two most encodings used in the binary representation of a CSD digit (1¯  stands for  1). In this paper, encoding 2 is used.Encoding 1 Encoding 2  y i  y si  y di  y si  y di 0 00 001 01 01¯ 1 11 10 0 0 1 0 1 0 1 1 10 0 1 0 1 1 0 0 10 0 1 1 0 1 0 0 10 1 0 1 0 1 0 0 1 Fig. 1.  Conversion process from binary to CSD code. G.A. Ruiz, M. Granda / Microelectronics Journal 42 (2011) 1090–1097   1091  Since  y i  takes one of the three values {0, 1, 1¯ }, two bits {  y si ,  y di  }are necessary to encode it, which are defined from Table 2 as  y di  ¼  x i þ 1 ð  x i    c  i  1 Þ ¼  x i þ 1 d i  y si  ¼  x i þ 1 ð  x i    c  i  1 Þ ¼  x i þ 1 d i (  ð 10 Þ For the sake of clarity, the following example describes thedifferent signals used in the CSD recoding:  X   ¼ 001010111 Carry ¼ 011111110 D ¼ 010101001 Y   ¼ 010101001In the case of a  n -bit two’s complement binary number  X  , theCSD representation is given by Y   ¼   x n  1 U 2 n  1 þ X n  2 i  ¼  0  x i U 2 i ¼ X n  1 i  ¼  0  y i U 2 i ð 11 Þ here, only  n  CSD digits are necessary as the value of the binarynumber is limited to [  2 n , 2 n  1 ]. Negative integers in CSD can beobtained trivially from their positive counterpart by changing thesigns of all nonzero digits. For example, the CSD code 0101represents the decimal number 3, while 0101 represents thenumber   3. Therefore, the conversion of a negative  n -digit two’scomplement binary number  X   into its CSD representation can beperformed from the well-known property    X   ¼  X  þ 1. Then refor-mulating the former equations for the case of a binary number  X   ina two’s complement representation, the conversion into its CSDrepresentation is given by t  i  ¼  x i    x n  1 ,  i o n  1  ð 12 Þ c  0 i  ¼ t  i þ 1 t  i  þð t  i þ 1  þ t  i Þ c  0 i  1 ,  being  c  0 1  ¼  x n  1  ð 13 Þ where  x n  1  represents the sign of   X  . From (13),  c  ’ i  propagates  c  i  orits complement depending on sign of the  X   because of all inputs arecomputed according to (12). Therefore, another way to express  c  ’ i  is c  0 i  ¼  x n  1    c  i  ð 14 Þ Applying these definitions, we get d i  ¼ t  i    c  0 i  1  ¼ ð  x i    x n  1 Þ  ð  x n  1    c  i  1 Þ ¼  x i    c  i  1  ð 15 Þ This means that the definition of   D  is independent of sign  X  . Ina similar way, the expression of   Y   is the same as that in (10) as  y di  ¼ t  i þ 1 d i  ¼ t  i þ 1 ð t  i    c  0 i  1 Þ ¼ ð  x i þ 1    x n  1 Þðð  x i    x n  1 Þ   c  0 i  1 Þ ¼  x i þ 1 d i  y si  ¼ t  i þ 1 d i  ¼ t  i þ 1 ð t  i    c  0 i  1 Þ ¼ ð  x i þ 1    x n  1 Þðð  x i    x n  1 Þ   c  0 i  1 Þ ¼  x i þ 1 d i ( ð 16 Þ Fig. 2 shows the circuit to convert a  n ¼ 6 digit binary numberinto its CSD representation according to Eqs. (8)–(10), valid forboth unsigned and two’s complement binary numbers. The onlydifference arises in the last CSD digit. By introducing an extra signextension,  x n ¼ 0 for unsigned numbers and  x n ¼  x n  1  for two’scomplement numbers, the last section changes depending on thesign of   X   in the following general expression:For an unsigned number  X   y dn  1  ¼ d n  1  y sn  1  ¼ 0  y dn  ¼ d n  ¼ c  n  1  ¼  x n c  n  2  y sn  ¼ 0 8>>>>><>>>>>: ð 17 Þ For a signed number  X   y dn  1  ¼  x n d i  ¼  x n  1 c  n  2  y sn  1  ¼  x n d i  ¼  x n  1 c  n  2 (  ð 18 Þ For unsigned  X  ,  n þ 1 CSD digits are necessary to represent thatbinary number. However, as it is a positive number the two MSBdigits of CSD are also positives and, indeed, only their positivedata parts are necessary as shown in Eq. (17); the negative part isalways zero. For signed numbers, only  n  CSD digits are used andthe last digit is computed according to Eq. (18). As can be seen in Fig. 2, the critical path of the circuit is fixed by the propagation of the carry signal, in a similar way to a conventional ripple-carryadder. There is a clear similarity between the carry definition inconventional adders and the definition of that carry in Eq. (8). Thissuggests that implementation of fast CSD converters should bebased on fast well-known carry look-ahead structures used inaddition. 3. New CSD recoding  In the definition of carry in Eq. (8), two adjoining carries sharethe same input variable. This means that the same input  x i  is usedin the generation of both carries  c  i  1  and  c  i . This characteristicallows the algebraic expressions of carry generation to be simpli-fied in order to obtain efficient circuits.  Table 2 CSD coding.  x i þ 1  x i  c  i  1  y i  c  i  Comments0 0 0 0 0 String of 0s0 0 1 1 0 End of 1s0 1 0 1 0 A single 10 1 1 0 1 String of 1s1 0 0 0 0 String of 0s1 0 1 1¯  1 A single 01 1 0 1¯  1 Beginning of 1s1 1 1 0 1 String of 1s Fig. 2.  Schematic circuit for the conversion of a binary number into its CSD representation ( n ¼ 6). G.A. Ruiz, M. Granda / Microelectronics Journal 42 (2011) 1090–1097  1092  Let  X   be a  n -digit binary number. If we define two signals,  H  ¼ { h 0 , h 1 , y , h n  1  }  and  K  ¼ { k 0 , k 1 , y , k n  1  } , as h i  ¼  x i h i  1 ,  for  i  odd  x i  þ h i  1 ,  for  i  even (  ð 19 Þ k i  ¼  x i  þ k i  1 ,  for  i  odd  x i k i  1 ,  for  i  even (  ð 20 Þ with  h  1 ¼ 0 and  k  1 ¼ 0. Then  c  i  can be formally expressed interm of odd or even index  i  by means of the following recursiverelation: c  i  ¼ h i  þ  x i þ 1 k i  ¼ h i  þ k i þ 1 ,  for  i  odd  x i þ 1 h i  þ k i  ¼ h i þ 1  þ k i ,  for  i  even (  ð 21 Þ A demonstration by induction of this equation can be found inappendix A of Ref. [36]. Moreover,  h i  and  k i  have the followingproperties:For  i  odd a Þ  h i k i  ¼ h i b Þ  h i k i  ¼ 0 c  Þ  h i  þ k i  ¼ 1 d Þ  h i  þ k i  ¼ k i 8>>>><>>>>: ð 22 Þ For  i  even a Þ  h i k i  ¼ k i b Þ  h i k i  ¼ 0 c  Þ  h i  þ k i  ¼ 1 d Þ  h i  þ k i  ¼ h i 8>>>><>>>>: ð 23 Þ Demonstrations of these properties can be found in appendix Bof Ref. [36]. However, using these properties, Eq. (21) can betransformed into another compact form as c  i  ¼ h i  þ  x i þ 1 k i  ¼ h i þ 1 k i ,  for  i  odd  x i þ 1 h i  þ k i  ¼ h i k i þ 1 ,  for  i  even (  ð 24 Þ For the sake of clarify, the definition of the carry based on  H  and  K   signals for  n ¼ 4 are described. From Eq. (8), we get c  0  ¼  x 1  x 0 c  1  ¼  x 1  x 2  þð  x 1  þ  x 2 Þ c  0  ¼  x 1  x 0  þ  x 2  x 1 c  2  ¼  x 2  x 3  þð  x 2  þ  x 3 Þ c  1  ¼  x 3 ð  x 2  þ  x 1  x 0 Þþ  x 2  x 1 c  3  ¼  x 3  x 4  þð  x 3  þ  x 4 Þ c  2  ¼  x 3 ð  x 2  þ  x 1  x 0 Þþ  x 4 ð  x 3  þ  x 2  x 1 Þ From the recursive property in the definition of signals  H   and  K   of Eqs. (19) and (20), it is straightforward to obtain thefollowing expressions h  1  ¼ 0 h 0  ¼  x 0  þ h  1  ¼  x 0 h 1  ¼  x 1 h 0  ¼  x 1  x 0 h 2  ¼  x 2  þ h 1  ¼  x 2  þ  x 1  x 0 h 3  ¼  x 3 h 2  ¼  x 3 ð  x 2  þ  x 1  x 0 Þ h 4  ¼  x 4  þ h 3  ¼  x 4  þ  x 3 ð  x 2  þ  x 1  x 0 Þ k  1  ¼ 0 k 0  ¼  x 0 k  1  ¼ 0 k 1  ¼  x 1  þ k 0  ¼  x 1 k 2  ¼  x 2 k 1  ¼  x 2  x 1 k 3  ¼  x 3  þ k 2  ¼  x 3  þ  x 2  x 1 k 4  ¼  x 4 k 3  ¼  x 4 ð  x 3  þ  x 2  x 1 Þ Therefore, from Eqs. (21) and (24), the carry can be expressedin terms of those signals as c  0  ¼ h 1  þ k 0  ¼  x 1  x 0  þ 0 ¼ h 0 k 1  ¼  x 0  x 1 c  1  ¼ h 1  þ k 2  ¼  x 1  x 0  þ  x 2  x 1  ¼ h 2 k 1  ¼ ð  x 2  þ  x 1  x 0 Þ  x 1 c  2  ¼ h 3  þ k 2  ¼  x 3 ð  x 2  þ  x 1  x 0 Þþ  x 2  x 1  ¼ h 2 k 3 c  3  ¼ h 3  þ k 4  ¼  x 3 ð  x 2  þ  x 1  x 0 Þþ  x 4 ð  x 3  þ  x 2  x 1 Þ ¼ h 4 k 3 The variable  D  in Eq. (9) can be directly obtained from  H   and  K  without it being necessary to generate  c  i . If   i  is odd, this meansthat  i  1 is even, we obtain d i  ¼  x i    c  i  1  ¼  x i c  i  1  þ  x i c  i  1  ¼  x i U  x i h i  1  þ k i  1  þ  x i ð  x i h i  1  þ k i  1 Þ¼  x i ð h i  1  þ k i  1 Þþ  x i k i  1  ð 25 Þ In Eq. (23), we get  h i  1 þ k i  1 ¼ h i  1  and  h i  1 k i  1  ¼ 0. Then,applying these properties to Eq. (25), it can be transformed as d i  ¼  x i h i  1  þ  x i k i  1  ¼ ð  x i  þ h i  1 Þð  x i  þ k i  1 Þ ¼  x i h i  1 ð  x i  þ k i  1 Þ ¼ h i k i ð 26 Þ For  i  even, and likewise, we obtain d i  ¼ h i k i  ð 27 Þ However, the variable  Y   for the CSD recoding in terms of signals  H   and  K   can be expressed as  y di  ¼  x i þ 1 d i  ¼  x i þ 1 h i k i  ¼ h i þ 1 k i ,  for  i  odd  x i þ 1 h i k i  ¼ h i k i þ 1 ,  for  i  even (  ð 28 Þ  y si  ¼  x i þ 1 d i  ¼  x i þ 1 h i k i  ¼ h i k i þ 1 ,  for  i  odd  x i þ 1 h i k i  ¼ h i þ 1 k i ,  for  i  even (  ð 29 Þ The proposed equations based on signals  H   and  K  , which arefunctionally equivalent to two carries, lead to an efficient hard-ware implementation of CSD recoders. Fig. 3 shows the proposedimplementation for the conversion of a 5-bit binary number  X  into its equivalent CSD representation. These signals can becomputed by two parallel and independent paths of simple ANDand OR gates in a ripple configuration. As a result, the critical pathis reduced and the hardware implementation is minimized incomparison with other structures derived from conventionaladders. The main body of this circuit is made up of alternative Fig. 3.  Proposed circuit for the conversion of a binary number into its CSD representation ( n ¼ 6). G.A. Ruiz, M. Granda / Microelectronics Journal 42 (2011) 1090–1097   1093
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