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Pll Summary

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some simple notes for the beginnening
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  Pll System :   1.what is pll , differ from wire ?2.phase Detector basics : xor,Model3.type1 pll loop operation : lock condition(settles,transient beha!ior wa!eforms. .what is loop filter and its trade offs ?low pass filter a!era#e extractor of $hase detector o%tp%t. Trades : 1. order of filter  &n!erse prop. with output ripples .b%t the order is limited by stability  2. BW  in!ersely with ripple attenuation  b%t prop.'o settling speed. .)co type and model ? *ffect of +ipples at o%tp%t of filter ?.why %se laplace model?open loop and closed '- of the type1 ?.what is type and order of pll define ? Type : no of nonlossless inte#rators. order : order of lossy /$-.0. $M of type1 order1 pll ?.&ss%es: 1. Reduce spur level at output of filter  : 1..first order filter with low c%toff fre. $M4  +in#in# and slow loop.1.5.second order more $M red%ction and may be %nstable.2. cycle slipping : at large change in divider. 6hen phase acc%mlation hi#her than $& . 'ake lon# time tosettle and may not lock (lock ran#e. Type 11 charge pump pll : 1.PFD : pros: 1.comparison +an#e inc. 2.phase error is asymmetrical aro%nd 7ero 3. $// will always relock.8omparin# type & and && : 9(s , D8 #ain of 9(s,phase error at $D inp%t , !lpf ran#e that can span, pfd and cp model . &t s%ffers from rin#in# at the o%tp%t beca%se $M; . <o we sho%ld ha!e a pole and a 7ero.'he commonly %sed $-D=8$ : 82 4 81 and the closed loop response   !aliditiy of linear model if time #ran%larities inherient in the wa!eform similar respect to time scale : wc 4 wref>1; cross o!er or loop 56.Max phase mar#in when wc #eometric mean of (wp,w7 so $M max f%nction in c1>c2 Phase noise:  8$:dominant in band, )8 : o%t of band.<DM:shapes noise and athi#h fre%ency.1. $-D=8$=di!ider noises will be low passed. 2. filter noise is band passed3. )co noise will be hi#h passed. <elect a $M of  which implies a wn>wc and @ at their c%r!es intersection with the $M . nd also to ha!e #ood approx relation of wc and w3db@;., c1>c22;settlin# time : time re%ired to char#e the capacitor that stores !co t%nin# ran#e. n our graduation pro!ect :  &<M band $// ,/ow &- +ecei!er Design steps : 1.choose the compliance ran#e : inp%t !olta#e t%nin# for !co and then A)8.2.choose $M to a!oid peakin#.3.wc  1>settlin# time B 1>wc choose for certain noise and sp%r atten%ation. .loop filter !al%es : accord to #ain and $M and 56.Di!ision +atio by -o%t and -ref relation. nd channel spacin# for the type.<DM order and 8$ c%rrent accord to noise atten%ation re%ired.<DM 3 rd  order to decrease in band noise and Di!ision +atio : .30 B 1.30  y #or$ : 1.Divide by t#o %& generator :1.' m()*'+f)1.,-)/++ mvpp diff 1.0 de#ree &C mismatch and stable across corners. *.Feedbac$ dividers : D 8M/ as 1 st Di!ide by 2 >3 circ%it and other as 8M< Di!iders to achie!e a di!ision ratio from  to 1 a 8M/ to 8moscirc%it is interfacin# these two sta#es .we %se only one 8M/ as Max inp%t fre%ency is 1.03 9E after 1 sta#e max o%tp%t is abo%t 1 M97 which is less than max operatin# fre%ency of 8Ms ato%r 13; n technolo#y (with reasonable dynamic power.it cons%mes abo%t 1. m and noise floor F1 d5c>9E as noise floor , it is well tested across corner analysis.
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