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verilog 1

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verilog 1
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   http://hdlplanet.tripod.com/verilog/verilog-manual.html 1.SIMULATION OF LOGIC GATES  module logicgates(in1,in2,out1,out2,out3,out4,out5,out6,out7, out8); input in1,in2; output out1,out2,out3,out4,out5,out6,out7,out8; assign out1=in1&in2; assign out2=in1|in2; assign out3=~(in1); assign out4=~(in2); assign out5=~(in1&in2); assign out6=~(in1|in2); assign out7=in1^in2; assign out8=~(in1^in2); endmodule 2.1. SYNTHESIS OF FULL ADDER  module fulladder(in1,in2,in3,sum,carry); input in1,in2,in3; output sum,carry; assign sum=(in1^in2)^in3;  assign carry=((in1&in2)|(in1&in3)|(in2&in3)); endmodule 2.2. SYNTHESIS OF HALF ADDER  module halfadder(in1,in2,sum,carry); input in1,in2; output sum,carry; assign sum=(in1^in2); assign carry=in1&in2; endmodule 3. 12 BIT SERIAL ADDER  module sadd(sum,carry); output[11:0]sum; output[3:0]carry; reg[11:0]sum; reg[3:0]carry; reg[11:0]in1=12'b111100101100;//F2C reg[11:0]in2=12'b110111000101;//DC5 reg[11:0]in3=12'b000100110011;//133 reg[11:0]in4=12'b010101101001;//569 reg[11:0]in5=12'b101001000111;//A47 reg[11:0]in6=12'b011010001101;//68D reg[11:0]in7=12'b100111001111;//9CF reg[11:0]in8=12'b111001110110;//E76 reg[12:0]temp=13'b1000000000000; reg[15:0]temp1=16'b1000000000000000; wire[11:0]sum1; reg[12:0]a1,a2,a3,a4,a5,a6,a7,a8; reg[2:0]car0=3'b000; wire[2:0]car1,car2,car3,car4,car5,car6,car7,car8,car9,car10,car11,car12; reg[14:0]c=15'b000000000000000; reg[15:0]res=16'b0000000000000000;   always@(temp,in1,in2,in3,in4,in5,in6,in7,in8) begin a1<=temp-in1; a2<=temp-in2; a3<=temp-in3; a4<=temp-in4; a5<=temp-in5; a6<=temp-in6; a7<=temp-in7; a8<=temp-in8; end fhadd bitadd1(a1[0],a2[0],a3[0],a4[0],a5[0],a6[0],a7[0],a8[0],car0,sum1[0],car1); fhadd bitadd2(a1[1],a2[1],a3[1],a4[1],a5[1],a6[1],a7[1],a8[1],car1,sum1[1],car2); fhadd bitadd3(a1[2],a2[2],a3[2],a4[2],a5[2],a6[2],a7[2],a8[2],car2,sum1[2],car3); fhadd bitadd4(a1[3],a2[3],a3[3],a4[3],a5[3],a6[3],a7[3],a8[3],car3,sum1[3],car4); fhadd bitadd5(a1[4],a2[4],a3[4],a4[4],a5[4],a6[4],a7[4],a8[4],car4,sum1[4],car5); fhadd bitadd6(a1[5],a2[5],a3[5],a4[5],a5[5],a6[5],a7[5],a8[5],car5,sum1[5],car6); fhadd bitadd7(a1[6],a2[6],a3[6],a4[6],a5[6],a6[6],a7[6],a8[6],car6,sum1[6],car7); fhadd bitadd8(a1[7],a2[7],a3[7],a4[7],a5[7],a6[7],a7[7],a8[7],car7,sum1[7],car8); fhadd bitadd9(a1[8],a2[8],a3[8],a4[8],a5[8],a6[8],a7[8],a8[8],car8,sum1[8],car9); fhadd bitadd10(a1[9],a2[9],a3[9],a4[9],a5[9],a6[9],a7[9],a8[9],car9,sum1[9],car10); fhadd bitadd11(a1[10],a2[10],a3[10],a4[10],a5[10],a6[10],a7[10],a8[10],car10,sum1[10],car11); fhadd bitadd12(a1[11],a2[11],a3[11],a4[11],a5[11],a6[11],a7[11],a8[11],car11,sum1[11],car12); always@(car12,sum1,temp1,c,res) begin c<={car12,sum1}; res<=temp1-c; sum<=res[11:0]; carry<=res[15:12]; end endmodule //fhadd(8 bit addition) module fhadd(i1,i2,i3,i4,i5,i6,i7,i8,cp,s,c); input i1,i2,i3,i4,i5,i6,i7,i8; input [2:0]cp;  output s; output [2:0]c; reg s; reg [2:0]c; reg [3:0]s2; wire [3:0]s1; wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18; wire ca1,ca2,ca3,ca4,ca5,ca6,ca7,ca8,ca9,ca10,ca11,ca12; wire ca13,ca14,ca15,ca16,ca17,ca18,ca19,ca20,ca21,ca22; hala ha1(i1,i2,x1,ca1); hala ha2(x1,i3,x2,ca2); hala ha3(x2,i4,x3,ca3); hala ha4(x3,i5,x4,ca4); hala ha5(x4,i6,x5,ca5); hala ha6(x5,i7,x6,ca6); hala ha7(x6,i8,s1[0],ca7); hala ha8(ca1,ca2,x7,ca8); hala ha9(ca3,x7,x8,ca9); hala hal0(ca4,x8,x9,ca10); hala hal1(ca5,x9,x10,ca11); hala hal2(ca6,x10,x11,ca12); hala hal3(ca7,x11,s1[1],ca13); hala hal4(ca8,ca9,x12,ca14); hala hal5(ca10,x12,x13,ca15); hala hal6(ca11,x13,x14,ca16); hala hal7(ca12,x14,x15,ca17); hala hal8(ca13,x15,s1[2],ca18); hala hal9(ca14,ca15,x16,ca19); hala ha20(ca16,x16,x17,ca20); hala ha21(ca17,x17,x18,ca21); hala ha22(ca18,x18,s1[3],ca22); always@(s1,cp,s2) begin s2<=s1+cp; s<=s2[0]; c<=s2[3:1];
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