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VHDL sample ptograms

A few sample programs using VHDL
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    Expt. No. : 01 LOGIC GATES Date : AIM To verify the functionalities of XOR & AND logic gates using ModelSim software. CODE xor2.vhdl library ieee; use ieee.std_logic_1164.all; --entity declaration  entity xor2 is  port(a,b : in BIT; y : out BIT); end xor2; --architecture declaration  architecture dataflow of xor2 is  begin y <= a xor b; end dataflow; and2.vhdl library ieee; use ieee.std_logic_1164.all; --entity declaration  entity and2 is  port(a,b : in BIT; y : out BIT); end and2; --architecture declaration  architecture dataflow of and2 is  begin y <= a and b; end dataflow;   SAMPLE OUTPUT  xor2.vhdl and2.vhdl RESULT The functionalities of logic gates using their truth tables had been verified successfully using VHDL  programming.    Expt. No. : 02 HALF ADDER Date : AIM To verify the functionality of half adder in structural  and dataflow  architectures using ModelSim software. CODE half_adder.vhdl library ieee; use ieee.std_logic_1164.all; entity half_adder is  port(a,b : in BIT; sum,carry : out BIT); end half_adder; --architecture declaration  –    dataflow architecture dataflow of half_adder is  begin sum <= a xor b; carry <= a and b; end dataflow; --architecture declaration  –    structural architecture structural of half_adder is component xor2  port(a,b: in BIT; y: out BIT); end component; component and2  port(a,b: in BIT; y: out BIT); end component;  begin x1: xor2 port map(a,b,sum); x2: and2 port map(a,b,carry); end structural;    SAMPLE OUTPUT RESULT The functionality of half adder using dataflow and structural architectures is verified successfully using VHDL programming.
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