# VL7301 Testing of VLSI Circuits

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Year/Branch: II-ME-VLSI Design Course Title & Code: VL9201  –   Testing of VLSI Circuits UNIT-1 BASICS OF TESTING AND FAULT MODELLING PART-A 1. What are the types of fault models?    Stuck-at fault    Bridging fault    Stuck-open fault 2. Define stuck-at fault? It is a faults in logic gates results in one of its inputs or output being fixed either a logic 0 (stuck¬at-0) or a logic 1 (stuck-at-1). 3. Define fault equivalence Two faults f and g are said to be functionally equivalent, iff Z f  (x) = Z g (x). 4. Define sensitized path? A path composed of sensitized lines is called a sensitized path. 5. State the lemma rule. Let G be the gate with inversion i and controlling value c, whose output is sensitized to a fault f(by a test t). 1. All inputs of G sensitized to f have the same value (say a). 2. All inputs of G not sensitized to f (if any have value c). 3. The output of G has value a. 6. What is redundancy? A combinational circuit that contains an undetectable struck fault is said to be redundant. 7. Define fault dominance. Let Tg be the set of all tests that detect a fault g. we say that a fault f dominates the fault g iff f and g are functionally equivalent under To. 8. Give the algorithm for one pass strategy. for every event (i,v,')pending at the current time t  begin v(i) = Vi' for every j on the fanout list of i  begin update input values of j  Vi'=evaluate (j) if vi *Isvo then begin schedule (j, vo) for time t+d(j) lsv(j vo) end end 9. What are the proper lies of Single (Rote) stuck-at Bob? Only one line is faulty The faulty line is permanently set to 0 or 1.The fault can be at an input or output of a gate Simple logical model is independent of technology details It reduces the complexity of fault description Algorithms. 10. Define bridging faults and mention its types? shorts between two or more signal lines are called as bridging faults. It can be classified into three types. Input bridging faults Feedback bridging faults  Not Feedback bridging faults II. What is the difference between transient and inrynnittent faults? Trans Wry fault -recurring faults and it is caused by power supply fluctuation. An intermittent Fault is a recurring (reappear on a regular basis) and it is caused by loose connection, poor design and some environmental conditions. PART-B I. Disciss the types of fault models used in digital circuits at different levels of design. 2. a. Explain how gate level event driven simulation is caned out. (10) b. Explain about die delay modeis.(6) 3. Discuss on the various types of fault simulation techniques used in digital circuits. 4. Discuss on the faults in digital circuit and its modeling at various levels of IC diagram. 5. Explain about Bridging faults, Delay faults and temporary faults.   UNIT-2 TEST GENERATION PART-A 1. Mention any four methods used in test generation for combinational circuits? One-Dimensional path sensitization Boolean Difference D-Algorithm PODEM  —   AlgoOthm 2. What is controllability and observability? Controllability is an ability to apply test patterns to the inputs of a sub circuit via primary of the circuit. Observability is an ability to observe Me response of a sub circuit via the primary output of the circuit. 3. Define Backtrace The procedure for obtaining a primary input assignment given an initial objective. It is known as Backtrace. 4. Mention any two methods used M test generation for sequential circuits    State table verification    Testing of sequential circuits as iterative combinational circuits 5. Draw the hardware model for delay fault testing? 6. What Is mean by homing sequence? To design checking experiment it is necessary to blow the initial state of the network, which is determined by distinguish or homing sequence. 7. List out the three phases of checking experiment? 1.   Initialization phase 2.   State identification phase 3.   Transition verification phase 8. List out the advantages of LSSD techniques,  The correct operation of the logic network is independent of nc characteristics such as clock edge rise tine and fall time. News is combinational in name as far as test generation and testing is concerned. The elimination of all hazards and races greatly simplifies both test generation and fault PART-B I. Explain 17-algoritInn and using that algorithm fuld a tem vector for the given BIM in die circuit shown in Fig. I. 2. Explain how test sequence is generated in sequential circuits using checking experiments with example. 3. Explain PODEM algorithm and using PODEM find a test vector for the fault 'X S/O' in the circuit shown in Figure 4. Explain how sequential circuits are tested using time frame expansion method. 5. Problems in Boolean differences (8 Marks) and Properties of Boolean differences (8marks) 6. Explain the following i) Ad-hoc design rules for improving testability and ii) LSSD Design rules.

Jul 23, 2017

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