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A Tutorial for Key Problems in the Design of Hybrid Hierarchical NoC Architectures With WirelessRF

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un tutorial para problemas de diseno de NOC
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  Smart Computing Review, vol. 3, no. 6, December 2013 This research was supported by the Beijing Municipal Natural Science Foundation (No.4122010, 2012.1 - 2014.12). DOI: 10.6029/smartcr.2013.06.004 425 Smart Computing Review     A Tutorial for Key Problems in the Design of Hybrid Hierarchical NoC  Architectures with Wireless/RF Chunhua Xiao , Zhangqin Huang, and Da Li Embedded Software and System Institution, Beijing University of Technology / 100022, Beijing, CHINA / xiaochh@emails.bjut.edu.cn *  Corresponding Author: Chunhua Xiao   Received August 15, 2013; Revised October 31, 2013; Accepted November 8, 2013; Published December 19, 2013    Abstract: As processing nodes scale up, it is difficult for traditional electronic networks to supply on-chip communication efficiently due to unacceptable latency, plus power and area consumption. Alternative interconnects, such as radio frequency interconnect (RF-I) and optical interconnect, have been explored as interconnection backbones. Hybrid hierarchical architectures with both traditional interconnects and emerging interconnects have been widely adopted to get excellent trade-off between latency and power. The hybrid hierarchical architecture with a wireless/RF-I  backbone is more cost-efficient and feasible due to advantages in complementary metal oxide semiconductor compatibility, compared with other alternative interconnects, and has become one of the mainstreams of chip multi-processor systems. However, how to efficiently utilize the wireless/RF-I backbone is a new challenge for designers. Based on analysis of existing typical hybrid hierarchal wireless/RF-I architectures (HHWAs), the key problems in the Design of HHWAs are proposed here, and related potential solutions are provided. In particular, strategies for resource management of wireless/RF-I are explored in detail, and different solutions are discussed. This work is expected to serve as a basis for future HHWA designs. Keywords:  Network-on-chip, radio frequency interconnect, wireless interconnect  Xiao et al.: A Tutorial for Key Problems in the Design of Hybrid Hierarchical NoC Architectures with Wireless/RF 426 Introduction s we enter the era of multiple cores and beyond, the number of cores, coprocessors, and on-chip accelerators grows rapidly. The dramatic increase of these processing elements (PEs) imposes a tremendous challenge for on-chip communication that demand high performance, including lower latency and higher bandwidth, but also minimal  performance per energy/area. According to the International Technology Roadmap for Semiconductors (ITRS) [1], improving characteristics of metal wires will no longer satisfy performance requirements, and new interconnect paradigms are needed. Different revolutionary approaches, such as optical interconnect [2][3], radio frequency interconnect (RF-I) [4][5][6], and wireless interconnect with complementary metal oxide semiconductor (CMOS) ultra wide band (UWB) technology [7][8], have been explored. But these emerging interconnects have associated antenna and transceiver area, extra integrated components and power overheads, and thus need to be placed and used optimally to achieve the best  performance without undue overhead [9][10]. Although the traditional planar metal interconnects suffer from limitations arising from multi-hop communication, which result in high latency and power consumption, they are still highly effective and suitable for short distances. The vast improvements in CMOS technology have led to wires with only 0.18 pJ/bit of energy consumption at 1 mm for a 32 nm technology design [11]. Based on these reasons or technology problems, many researchers adopted hybrid hierarchical wireless/RF-I architectures (HHWAs) to get excellent trade-offs between latency and power with limited extra cost [12][13][14][15][16]. HHWA is characterized by local traditional wired interconnection and global wireless/RF-I interconnection, and provides some unique benefits including the following: (1) Instead of multi-hop in traditional interconnection, wireless/RF-I implements one hop for long distance communication, which alleviates  power consumption while providing high bandwidth and low latency without excessive overhead. (2) Taking full advantage of traditional networks on a chip (NoCs) and emerging interconnects, HHWA employs their respective merits. (3) Compared with optical interconnects in hybrid architectures, using wireless/RF-I as a global communication backbone attains better feasibility and cost-efficiency due to an advantage in CMOS compatibility. As an architecture composites emerging technologies and traditional interconnects, new design challenges arise that might be bottlenecks to performance improvement. This work explores the key problems in HHWA designs and provides related potential solutions, which is expected to serve as basis from which to work towards future HHWA design. The rest of the paper is organized as follows. In Section 2, we provide a brief overview of the new alternative interconnect technologies (wireless and RF-I) and how they can be leveraged for on-chip communication. Based on the availability of these two interconnect technologies, we discuss the topology of HHWAs and explore the existing typical HHWAs in Section 3. Due to importance of wireless/RF-I resource management in HWWAs, we did an in-depth survey and analyze the resource arbitration mechanisms in Section 4. In Section 5, we summarize the key problems in HHWA design and  provide related feasible solutions. Finally, we conclude our work in Section 6. RF-I/Wireless ■  RF-I Radio frequency interconnect has been proposed as a high-aggregate bandwidth, low-latency alternative to traditional interconnect [4][5][19]. Its benefits have been demonstrated for off-chip, on-board communication, as well as for on-chip interconnection networks [20][21][22]. Unlike conventional metallic wires that require charging an d discharging the whole wire to signify either ―0‖ or ―1‖, RF-I modulates information on an electromagnetic carrier wave that is continuously sent along the transmission line (Figure 1). RF-I has been projected to scale better than traditional RC wires in terms of delay and power consumption; it can allow signal transmission across a 400 mm2 die in 0.3 ns via propagation at the effective speed of light [5] as opposed to less than, or equal to, 4 ns on a repeated bus. Instead of trying to aggressively expand baseband bandwidth (which often involves power-hungry compensation techniques to achieve a flat channel frequency response), RF-I divides bandwidth into frequency domains, each becoming a narrow-band signal, which saves power. By doing this, RF-I also improves bandwidth efficiency by sending many simultaneous streams of data over a single transmission line. This particular technique is referred to as multi-band RF-I [6]. As shown in the Figure 2, there are N mixers on the transmitting (or Tx) side in multi-band RF-I, where N is the number of senders sharing the transmission line. Each mixer up-converts individual data streams into a specific channel (or frequency  band). On the receiver (Rx) side, N additional mixers are employed to down-convert each signal back to the srcinal data and N low-pass-filters (LPF) are used to isolate the data from residual high-frequency components. Based on shortcut selection, each transmitter or receiver in the topology will be tuned to a particular frequency (or disabled entirely) to implement our shortcuts [5][6]. A  Smart Computing Review, vol. 3, no. 6, December 2013 427 C $ $ C $ $ C $ $ C $ $ C $ $ C $ $ C $ $ C $ $ $ $ $ $ $ $ $ $$ $ $ $ $ $ $ $$ $ $ $ $ $ $ $$ $ $ $ $ $ $ $$ $ $ $ $ $ $ $M MMC Core  $ L2 cache bank  M Off-chip Memory controller RF-I transmission lineRF-I node M$ $ $ $ $ $ $ $ Router  CCCCCCCCC C C CC C C CCCCCCCCCC C C CC C C CCCCCCCCCC C C CC C C CCCCCCCCC   Figure 1.  RF-I transmission line in a chip multiprocessor system Figure 2.  A ten-carrier RF-I and corresponding waveform at the transmission line ■  Wireless Different from RF-I, the transmission channel does not need to be physically laid out for wireless interconnection, and the communication medium is free space [23]. Wireless communication can be over different frequency ranges, from several gigahertzes to thousands of gigahertz [24]. An on-chip antenna is always one of the most difficult, but very important, components that can be integrated on-chip for HHWAs, because passive devices such as inductors consume the dominant portion of the transceiver area. Fortunately, as CMOS technology improves, not only the size but also the cost of the antenna and required circuits will decrease dramatically, which provides the feasibility for integrating multiple on-chip antennas [12]. An example of the necessary components of wireless transceivers for millimeter wave (mm-wave) links in a chip multiprocessor system is shown in Figure 3. A metal zigzag antenna was demonstrated to support wireless network-on-a-chip (WiNoC) [25] and was used to design an mm-wave wireless NoC by Deb et al. [26]. As the transmission frequency increased to the terahertz range, carbon nanotubes (CNTs) were explored for the on-chip antenna [27], and the feasibility of designing a WiNoC was demonstrated  by Ganguly et al. [15]. Compared with RF-I, which needs the transmission line to span the entire chip area, communication routing is not limited by the physical channel for wireless interconnection. However, wireless interconnection faces interference challenges and cost problems, which are proportional to the communication distance.  Xiao et al.: A Tutorial for Key Problems in the Design of Hybrid Hierarchical NoC Architectures with Wireless/RF 428 C0C0 C1 C1 C0C0 C1 C1C3 C3 C2 C2C3 C3 C2 C2 Cluster 0: C0 AntennaSwithDriver Amplifier LNAModulator Carrier Frequency DemodulatorSerializer Deserializer   D a  t a   t o   b e   t r a n s m  i  t  t e  d  D a  t a   R e c e  i v e  d Transmitter SideReceiver Side   Figure 3.  An example of mm-wave links in a chip multiprocessor system Hybrid Hierarchical Wireless/RF-I Architectures ■  Topology Topology defines how channels and routers are connected in an interconnection network and determines the performance  bounds  —  including zero-load latency and network throughput [17]. As showed in Figure 4, A hybrid hierarchical wireless/RF-I network consists of two types of network: a local network, which uses traditional wire interconnects, and a global/express network, which uses wireless/RF-I. For a conventional NoC, there can be various topologies for a local network, such as mesh, centralized mesh, ring, star, etc. Each local network forms a subnet and is equipped with a wireless/RF-I access point (WAP). As long as the antennas are placed within communication range (or the RF-I is enabled  between them), only a single hop is needed for inter-subnet communication. All WAPs from all subnets are connected as a second-level network forming the global/express network. This upper level of the hierarchy can have various designs with different characteristics to achieve the full benefit of on-chip express networks. An important problem when creating an efficient global/wireless network is the placement of WAPs, which will greatly influence the trade-off between system performance and cost. If each PE is equipped with a WAP (each local network only consists of one node) and can communicate with any other node through the express wireless/RF-I, we can get the best system performance with low latency and high throughput. But the area cost may be unpalatable due to the equipment (antennas, transceivers, etc.). If too many PEs share a WAP, or if the WAP is placed improperly, performance improvement would be offset by induced overhead. Ganguly et al. induced small world theory to create an HHWA, and inserted wireless links through a simulated annealing  –   based algorithm to minimize the average distance (measured by the number of hops)  between all source and destination hubs [15]. Chang et al. used RF-I as an express shortcut between intensively communicated nodes with communication profiling of the application to accelerate and optimize region-to-region communication. They placed the RF-enabled routers in a staggered fashion to minimize the distance any given component would need to travel to reach the RF-I [16]. Different from related works, Lee [12] and Di Tomaso et al. [13] placed the WAPs at the center of concentrated mesh-based clusters to provide distributed wireless express pathways for inter-cluster, long-haul communication to support hundreds of PEs. ■  Existing Typical Architectures Chang et al. [16] exploited dynamic RF-I bandwidth allocation to realize a reconfigurable hierarchical network-on-a-chip architecture. As shown in Figure 5, this architecture uses a mesh topology as the baseline and places adaptive shortcuts as an RF-overlaid topology to match different communication demands of the applications. This approach selects shortcuts according the optimizing cost equation synthesized with application communication statistics. The selected shortcuts are implemented through RF-I enabled routers (standard routers extending a port as an RF-I interface). Each transmitter or receiver in the topology is tuned to a particular frequency (or disabled entirely) to offer a shortcut. To enable the new available paths (RF-I shortcuts) and also reduce the reconfiguration cost, the routing tables in all network routers will be updated before executing the application. A shortest path routing strategy is adopted with RF-I shortcuts to transmit packets. This dynamic allocation approach enables reconfiguring the topology via frequency band reassignment, thereby providing the benefits of adaptive routing without having to pay the cost of traversing extra channels [23].

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