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A 320 Gb/s-Throughput Capable 2 $\,\times\,$2 Silicon-Plasmonic Router Architecture for Optical Interconnects

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  > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1  Abstract   — We demonstrate a 2x2 silicon-plasmonic router architecture with 320Gb/s throughput capabilities for optical interconnect applications. The proposed router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2x2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multiplexing and header processing functionalities. We present experimental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two racetrack resonators of 5.5 μ m radius and 4 μ m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experimental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2x2 thermo-optic switch operation. The validity of our circuit-level modeled 2x2 thermo-optic switch is verified by means of respective full vectorial three-dimensional Finite Element Method (3D-FEM) simulations. The router setup is completed by means of two 4x1 SOI multiplexing circuits, each one employing four cascaded 2 nd  order micro-ring configurations with 100GHz spaced resonances. Successful interconnection between the DLSPP switching matrix and the SOI circuitry is performed through a butt-coupling design that, as shown via 3D-FEM analysis, allows for small coupling losses of as low as 2.2dB. The final router architecture is evaluated through a co-operative simulation environment, demonstrating successful 2x2 routing for two incoming 4-wavelength Non-Return-to-Zero (NRZ) optical packet streams with 40Gb/s line-rates.  Index Terms  — Dielectric-loaded surface plasmon polariton waveguide, optical interconnects, optical routing, racetrack/ring resonator, silicon-on-insulator, silicon multiplexer, thermo-optic switching. Manuscript received March 29, 2011. This work has been supported by the EC FP7-ICT project PLATON (Contract number 249135). S. Papaioannou, A. Miliou and N. Pleros are with the Department of Informatics, Aristotle University of Thessaloniki, Thessaloniki, Greece (e-mail: sopa@csd.auth.gr  ). K. Vyrsokinos is with the Informatics and Telematics Institute, Center for Research and Technology Hellas, Thessaloniki, Greece. O. Tsilipakos, A. Pitilakis and E.E. Kriezis are with the Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Thessaloniki, Greece. K. Hassan, J.-C. Weeber, L. Markey and A. Dereux are with the Laboratoire Interdisciplinaire Carnot de Bourgogne (ICB), UMR 5209 CNRS-Université de Bourgogne, 9 Av. A. Savary, BP 47 870, F-21078 Dijon Cedex, France. S. I. Bozhevolnyi is with the Institute of Sensors, Signals and Electrotechnics, University of Southern Denmark, Odense, Denmark. I.   I  NTRODUCTION  ith parallel processing being the accepted methodology for boosting High Performance Computing (HPC)  performance improvements, multiple processing cores are required to exchange a vast amount of information that cannot  be sustained by bandwidth-limited electrical interconnects [1]. Limitations in bandwidth and excessive energy as well as footprint requirements arising from electrical wiring have led to a clearly shaped roadmap for bringing optics “into-the- box”, designating the shift towards optical interconnect solutions as the most promising paradigm for accessing Exascale processing powers [2],[3]. In this perspective, silicon  photonics appears as the dominant technology platform for the realization of low-loss, chip-scale and CMOS-compatible optical interconnects [4],[5]. Silicon-on-Insulator (SOI) technologies have proven capable of hosting most of the critical functions required for optical interconnect applications [6], leading to remarkable achievements both with respect to chip-level transceiver [7],[8] and routing [9] circuitry applications. This progress has, in turn, spurred intense research towards next-generation Chip Multi-Processor (CMP) architectures relying on optical interconnect planes, clearly indicating the important size and energy savings when  properly adapting the architectural CMP framework to the operational requirements of photonics [10]-[13].  However, with chip size reduction and energy savings being the driving forces in next-generation optical interconnect technology, the emerging research discipline of plasmonics appears as a promising candidate for challenging the stronghold of silicon. Plasmonics relies on the propagation of electromagnetic waves known as Surface Plasmon Polaritons (SPPs) along a metal-dielectric interface, and is expected to access processing characteristics that lie beyond the reach of  photonics and electronics [14],[15]. Strong mode confinement available with SPP waves allows for the deployment of  photonic circuits with sub-wavelength dimensions, breaking thereby the size barriers of traditional diffraction-limited optics [16]. Moreover, the presence of metal-dielectric interfaces amidst SPP-based circuitry allows for a seamless interface between electrical and optical signals, providing in this way a natural energy-efficient platform for merging  broadband optical links with intelligent electronic processing. The low-power functional portfolio of plasmonics is especially pronounced in the case of Dielectric-Loaded SPP A 320Gb/s-throughput 2x2 Silicon-Plasmonic Router Architecture for Optical Interconnects S. Papaioannou, K. Vyrsokinos, O. Tsilipakos, A. Pitilakis, K. Hassan, J.-C. Weeber, L. Markey, A. Dereux, S. I. Bozhevolnyi, A. Miliou, E. E. Kriezis and N. Pleros  W  > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 (DLSPP) waveguides that rely on the use of dielectric loading atop of metal (gold) films [17],[18]. DLSPP structures can, in  principle, be designed for different functionalities by simply selecting the proper dielectric material. Significant progress has been reported in this direction during the last years, demonstrating a whole new class of passive DLSPP circuits [19]-[21] and the first important experimental and theoretical steps towards controlling plasmon propagation via the thermo-optic effect and realizing respective switching modules [22]-[25]. Their potential for reaching system-level applications has further been strengthened by the demonstration of their successful interconnection to different waveguide platforms, including optical fibers [26] and SOI waveguides [27], and by their recent utilization for power monitoring purposes [28].  However, the development of strategy for bringing DLSPP structures into practical system-level applications at chip-scale environments is still in its infant years, the main limiting factor certainly being their high propagation losses. Similar to most plasmonic structures, DLSPP waveguides restrict signal  propagation over a few tens of micrometers due to radiation absorption in metal (ohmic loss) [18]. One approach of dealing with plasmonic losses could be by using Long-Range SPP (LRSPP) waveguides [29],[30] that have also been shown to serve as the transmission platform in 4x2.5Gb/s interconnects [29]. This roadmap comes, however, at the expense of substantially increased plasmonic-circuitry footprints, since LRSPP waveguides require mm-large bend radii (due to their weak lateral confinement), that negates the circuit size advantages expected by the employment of  plasmonic technology. In this article, we demonstrate for the first time to our knowledge a system-level application perspective of DLSPP switching structures that can optimally exploit the circuit size and low-energy advantages of the DLSPP waveguide  platform. We present a 2x2 silicon-plasmonic router architecture that can provide up to 320Gb/s throughput capabilities, using a novel dual-ring 2x2 DLSPP thermo-optic switch residing on a SOI photonic motherboard. The SOI motherboard is responsible for signal multiplexing and header  processing operations, so that the high-loss but highly functional DLSPP elements are employed only where switching functionality is required, whereas all necessary  passive photonic circuitry relies on low-loss SOI waveguides. The dual-resonator DLSPP configuration is experimentally characterized as an add/drop filtering element employing two racetrack resonators of 5.5 μ m radius and 4 μ m-long straight sections and the experimental results are verified through circuit-level analytical expressions for its frequency-domain transfer function. We extend our circuit-level model towards designing a 2x2 thermo-optic dual-ring DLSPP switch and respective results are found to be in close agreement with rigorous full vectorial 3D-FEM simulations. The router setup is completed by two 4x1 SOI multiplexing circuits (SOI-MUX) that are designed to support multiplexing of four wavelength channels spaced at 100GHz and carrying 40Gb/s  Non-Return-to-Zero (NRZ) packet traffic each. Interconnection between the silicon and plasmonic modules is achieved by a butt-coupling technique numerically investigated through 3D-FEM simulations and shown to yield small coupling losses as low as 2.2dB for the case of rib SOI waveguides. The final router platform is evaluated through a co-operative simulation platform incorporating the DLSPP and SOI-MUX circuit-level models into the VPI photonic network tool, showing successful 2x2 routing of two incoming 4-channel optical streams. The rest of the paper is organized as follows: Section II describes the silicon-plasmonic router architecture, while Section III reports on the analysis of the dual-resonator DLSPP configuration. Sections IV and V present the 4x1 SOI-MUX layout and the silicon-plasmonic coupling approach, respectively. Finally, Section VI demonstrates simulation results for the complete 2x2 router architecture. II.   T HE S ILICON -P LASMONIC R  OUTER A RCHITECTURE  Figure 1 illustrates the block diagram of the proposed 2x2 silicon-plasmonic router platform. It employs two incoming optical streams, each one comprising four time-overlapping data wavelengths modulated with 40Gb/s NRZ packet traffic, so that every input port supports an aggregate traffic of 160Gb/s. A discrete wavelength is responsible for carrying the header pulse information for every incoming stream, specifying the required router output port. This multi-wavelength traffic format has been already shown to enable high throughput in SOI routing interconnects, allowing for  packet-rate headers that can be easily processed by low-speed electronic control circuitry [9]. The router architecture relies on a SOI motherboard for ensuring low-loss optical interconnectivity between the router subsystems, while serving as the hosting platform for all heterogeneous technologies, including the 4x1 SOI multiplexers, the 2x2 DLSPP switching matrix, the photodiodes (PDs) and the Integrated Circuit (IC) control electronics. The four data channels forming an incoming traffic stream are inserted through the respective router input ports and are multiplexed in a 4x1 SOI multiplexer. This multiplexed multi-wavelength data sequence will then follow the same route through the entire platform. The header section carrying the information about the router outgoing port is modulated on a Fig. 1. Layout of the 2x2 silicon-plasmonic router architecture.  > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3 separate wavelength channel that enters the router through a distinct input port. The header channel is then opto-electronically (O/E) converted in a low-speed PD conversion module that provides the respective electrical header pulses at its output. This electrical signal is launched as input in the IC electronic control circuit that is responsible for header  processing and control signal generation. The IC circuit has two input ports for receiving the addresses of both incoming optical streams and generates the appropriate electronic control signal for driving the 2x2 DLSPP switching module. The DLSPP-based switching matrix is the router’s core element, associating the incoming optical streams with the specified output ports; traffic streams #1 and #2 exit the router through the output ports #1 and #2, respectively, when the DLSPP matrix operates in its BAR state, whereas they exchange output ports when CROSS state operation of the DLSPP matrix is selected. BAR or CROSS state operation of the DLSPP unit is dictated by the electrical control signal  provided by the IC. The SOI waveguide technology relies on a rib design with 400nm width, 340nm height and a silicon slab layer of 50nm thickness in order to allow for the propagation of the Transverse Magnetic (TM) optical mode supported by the DLSPP structures. As no buffering modules are employed in the router platform, contention resolution relies on deflection- based strategies adopting a prioritization scheme for the incoming optical traffic streams. The higher priority packet will leave the router through the desired outgoing port, while the lower priority stream will be directed to the second output  port following an alternate route until its final destination [31].  III.   THE D UAL -R  ESONATOR DLSPP   S WITCH  Figure 2 depicts the layout of a dual-resonator DLSPP configuration that serves as the thermo-optic switching element. It comprises two perpendicularly intersecting DLSPP waveguides along with two diagonally positioned DLSPP racetrack resonators. A similar architectural design has been utilized using SOI waveguide technology for switching of multi-wavelength incoming traffic [9]. However, the SOI- based layout employs large ring radii in the range of tens of micrometers aiming at generating a discrete resonant peak per inserted wavelength. This approach cannot be adopted in the case of a DLSPP-based implementation due to the high  propagation losses of DLSPP structures. To this end,  broadband multi-wavelength operation of the respective 2x2 dual-ring DLSPP configuration dictates that all inserted wavelengths have to reside within the passband of a single resonance. This can be ensured using small ring radii values that additionally allows for low loss device functionality.  A.    Frequency Domain Transfer Function In the following, the frequency domain transfer function of this device when acting as a passive filtering element is analytically derived for both output ports 1 and 2, assuming an incoming electrical field  E  in1  inserted through input port 1. The two racetrack resonators are considered to be identical employing two straight waveguide regions of lengths  L 1  and  L 2  and a curved section of radius  R . The resonators are separated by the bus waveguides by gaps of size  g  u , with u  representing the couplers a , b , c  or d   shown in Fig. 2. Couplers a  and c  are associated with the straight sections of length  L 1 , while couplings at b  and d   are associated with the waveguide sections  L 2 . By denoting as  E  u1  and  E  u2  the two electrical fields arriving at the coupler u  and as  E  u3  and  E  u4  the electrical fields leaving the coupler, the following relationships are valid at each coupling region:  3  =     1  +     2  (1)  4  =     2  +     1  (2) with t  u  and ξ  u  representing the field transmission and coupling coefficients, respectively, satisfying the relation    = �  1  2  in the absence of coupling losses. The 90 o  crossing between the two intersected waveguides is considered to introduce a power crosstalk level equal to m , so as to take into account also realistic crossing implementations where no tapering treatment of the crossing region is used [25],[32]. Denoting as  E   x1  and  E   x2  the crosspoint input signals and as  E   x3  and  E   x4  the respective output signals, field  propagation at the crosspoint is governed by the following set of equations:  3  =  √  1  2  1  + √  −   2  (3)  4  =  √  1  2  2  + √  −   1  (4) with φ m  standing for the additional phase acquired by the crosstalk. The mathematical framework required for the transfer function extraction is completed by taking into account also the corresponding field propagation equations between all  possible successive coupling regions or waveguide-crossing transitions. The propagation of an electrical field from a starting location k   to an end point l   can be generally expressed through multiplication with a path coefficient    , so that    =       =  √  −  −   , with  L  being the waveguide distance, α  the power loss coefficient, and   =  2      the  phase acquired during propagation, where  λ  stands for the wavelength and n eff   for the effective refractive index. Fig. 2. Dual-resonator DLSPP-based filter layout.  > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 Applying equations (1) and (2) to all employed coupling stages, using equations (3) and (4) and exploiting the above set of elementary propagation relationships for all possible routes in the dual-resonator layout, the transfer function can be derived by means of algebraic calculations. Equations (5) and (6) provide the electrical field transfer functions for output  ports 1 and 2, respectively, where the input and output electrical fields  E  in1 ,  E  op1  and  E  op2  are  E  a2 ,  E  c4  and  E  b4 , respectively.  B.    Experimental and Theoretical Analysis of a Dual- Resonator DLSPP Add/Drop Filtering Element A dual-resonator DLSPP structure performing add/drop filtering has been fabricated by a process relying on electron- beam lithography (EBL). A glass substrate is cleaned and coated with a gold thin film with a thickness of 60nm. This thickness value prohibits strong radiation of the plasmonic mode within the substrate, allowing, however, for the detection of the mode by means of a sensitive Infra-Red (IR) Charge-Coupled Device (CCD) camera. The metal coated substrate is next spin-coated with a Poly-methyl-methacrylate (PMMA) resist at a nominal thickness of 560-580nm. The PMMA-coated substrate is then exposed to the electron beam and the exposed areas are subsequently dissolved. Figure 3(a) depicts the Scanning Electron Microscope (SEM) image of the fabricated dual-resonator DLSPP add/drop filtering element. Both racetrack resonators have a radius of  R= 5.5 μ m and straight waveguide region lengths of  L 1 = 4 μ m and  L 2 = 0 μ m. The gaps  g  a ,  g  b ,  g  c ,  g  d   between the racetrack designs and the respective intersected waveguide sections are 333nm, 328nm, 305nm and 384nm, respectively. Optical characterization has been performed by Radiation Leakage Microscopy (RLM). Plasmonic mode excitation is achieved by focusing the incident laser on one end of the input waveguides. The excited plasmonic mode radiates a fraction of its energy within the dielectric substrate at an angle corresponding to a numerical aperture of typically 1.2 to 1.3. The image is recorded by an IR CCD camera with high sensitivity through an oil immersion objective [24]. Figures 3(b)-(c) illustrate the RLM images obtained at operating wavelengths 1520nm and 1536nm, respectively. The 1520nm wave is exiting the device through its Drop-port, while the optical power at 1536nm emerges at the Through- port. The complete experimental transmission spectra obtained for both the Through and Drop ports of the DLSPP module over the entire 1500-1560nm spectral window are shown by the dotted lines in Fig. 4. A clear resonant behavior can be observed with the Free Spectral Range (FSR) of the Through- port resonances being equal to 36nm. The resonant dips at the Through-port have an Extinction Ratio (ER) of more than 35dB, while the corresponding ER value for the Drop-port resonant peaks is close to 18dB. Insertion losses (IL) for the Through and Drop ports are -10dB and -12dB, respectively. The broadband characteristics of the Through and Drop port resonances can be also clearly identified: the Drop resonance at 1520nm has a -3dB bandwidth close to 12nm, while the resonant dip of the Through port at the same wavelength ensures signal suppression by more than 12dB within a spectral band of 10nm. These values confirm the potential of dual-resonator DLSPP structures to perform as multi-wavelength add/drop filtering elements, indicating at the same time their multi-wavelength properties when used in thermo-optic switching arrangements. The experimental transmission spectra of the dual-resonator DLSPP add/drop filtering module have been successfully reproduced by means of circuit-level modeling exploiting the frequency-domain transfer function of the device provided by equations (5) and (6). The theoretically extracted Through and Drop port transmission curves are shown by the solid lines in     =  √ 1−2      −       (   −      )    (5)       =        −        −      �√   1−        +  +2−1          −      1−           (6)     =   1       31   31 + √       32   42   31  −   1       31   31 + √       31   41   42  −   (1  2  )           31   31   42   42   32   41   (7)   Fig. 4. Transmission spectra at Through and Drop ports of the dual-resonator DLSPP add/drop filter obtained by circuit-level modeling (solid lines) and experiment (dotted lines with markers). Inset depicts the effective refractive index for a straight DLSPP waveguide according to FEM eigenmode analysis. Fig. 3. (a) SEM image of the dual-resonator DLSPP add/drop filtering element, (b), (c) RLM images when light is guided to the Drop and Through  port, respectively.  > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 5 Fig. 4. Coupling coefficients of  2 = 0.6 ,  2 = 0.05 ,  2 = 0.62  and  2 = 0.01  have been used for the four coupling regions corresponding to the respective  g  a ,  g  b ,  g  c ,  g  d   gaps between racetrack and straight waveguides. The high values used for  2  and  2  coupling coefficients indeed correspond to the increased coupling owed to the 4 μ m-long sections, while the low-level coupling induced by the  L 2 = 0 μ m sections is effectively associated with the small  2  and  2  coupling coefficients. A crosstalk level m  of -15dB has been considered at the crosspoint between the two intersected waveguides, with the respective phase shift φ m  equaling π /2, as  predicted by 3D-FEM analysis [25].  The inset in Fig. 4 illustrates the effective refractive index n eff   versus wavelength curve that has been obtained by a FEM eigenmode solver for the case of a straight PMMA-loaded SPP waveguide of 500x600nm 2  cross-section, taking into account the material dispersion of gold [33]. However, a negative offset of 0.15 has been applied to this curve before being employed in the circuit-level model. The lower n eff   values required for optimal fitting between theory and experiment are  probably due to contributions by the racetrack bending and coupling sections that have different mode propagation characteristics compared to straight DLSPP waveguides. The agreement between theory and experiment can be confirmed with respect to all relevant parameters, including FSR, ER and resonant bandwidth characteristics. The slight irregularity in the Drop-port resonant shapes is also efficiently  predicted by theory. The irregularities at the Drop-port resonant peak shapes are the result of multiple wave interference taking place at this port, since optical crosstalk terms and optical waves srcinating after circulations in both racetrack structures are forced to interfere. Although the same  phenomenon occurs at the Through-port, the Through-port field component emerging without any recirculating experience is much stronger in power than the respective recirculating field constituents. Therefore, the final Through- port output signal is almost insensitive to this multi-wave interference, being in good agreement with respective 3D-FEM-based theoretical findings [25]. As such, circuit-level analysis can provide reliable response predictions using simple n eff   calculations derived by FEM eigenmode analysis for straight DLSPP waveguides instead of solving the entire electromagnetic problem for the complicated structure of dual-resonator DLSPP design. The deviations observed between circuit-level simulations and experiment at Through-port’s IL value owe presumably to measurement inaccuracies arising by the integration method employed for the optical power calculation in the RLM characterization process [24].  C.    Dual-Ring DLSPP as a 2x2 Thermo-Optic Switch The passive dual-resonator DLSPP structure performing as an add/drop filter can be transformed into an active switching element through the utilization of the thermo-optic effect [22].  DLSPP waveguides provide a natural interface for electrically addressing their operation exploiting thermo-optics by simply injecting an electrical current to the finite-width metallic stripe [22],[23],[25]. This yields a local temperature change in the  polymer loading that can be efficiently translated in resonance tuning and, subsequently, in a change in the device’s switching state. This technique enables the effective exploitation of the field enhancement at the metal-polymer interface towards requiring reduced power consumption. The thermo-optic effect has been employed in the implementation of various dynamic components based on the stripe SPP waveguide [34],[35] and has been also more recently utilized for the control of DLSPP waveguide ring resonator and Mach-Zehnder interferometric devices [23],[24]. A detailed theoretical investigation through 3D-FEM simulations of thermo-optically tunable DLSPP all-pass filters, including their temporal switching response, is presented in [22].  Following the good agreement obtained between experiment and circuit-level modeling in dual-resonator DLSPP designs acting as passive add/drop filtering modules, the circuit-level model can be used for reliable predictions of the dual-ring DLSPP’s thermo-optic switching behavior by utilizing the n eff   values calculated for both an unheated and heated DLSPP waveguide. The optimized operation of the dual-ring DLSPP structure as a 2x2 switch requires, however, a slightly different design compared to the layout shown in Fig. 2. Operation as a 2x2 switch implies a similar  performance for both input ports, indicating specific symmetry conditions in the design. This symmetry can be obtained only  by having identical coupling stages ( t  a , ξ  a ) and ( t  d  , ξ  d  ) and, subsequently, identical values for the coupling sections ( t  b , ξ  b ) and ( t  c , ξ  c ). This means that in the case of the layout shown in Fig. 2, coupling stages a  and d   should be associated with the same straight waveguide length  L 1  of the respective racetrack resonator and with identical gap values, so that also the remaining b  and c  coupling stages will be associated with the  L 2  racetrack regions and, again, identical gap values. As no experimental data have been so far reported on dual-ring DLSPP switching, the performance of the circuit-level modeled dual-ring DLSPP design when operating as a 2x2 thermo-optic switch has been evaluated in comparison with respective findings when 3D-FEM calculations are employed [25]. The 2x2 switch layout adopted in the 3D-FEM approach and used also in the circuit-level analysis is shown in Fig. 5(a), using a ring radius of 5.6 μ m and without employing a racetrack design, so that both  L 1  and  L 2  equal zero. The gap dimensions employed in the 3D-FEM model have been 300nm for the coupling stages a  and d   and 500nm for the coupling stages b  and c , respectively. The detailed material and geometrical parameters as well as the methodology adopted in the 3D-FEM analysis are documented in [25]. 
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