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A Built-In Self-Test Design With Low Power Consumption Based on Genetic

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The Ninth International Conference on Electronic Measurement & Instruments ICEMI’2009 A Built-in Self-test Design with Low Power Consumption Based on Genetic Algorithm Enmin Tan Li Wang School of Electronic Engineering, Guilin University of Electronic Technology, Guilin, 541004, China Email: tem0135@guet.edu.cn Abstract – A low peak power consumption built-in self-test (BIST) design based on genetic algorithm (GA), which is denoted by GAITPG, has been proposed in our previous study. This pape
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  The Ninth International Conference on Electronic Measurement & Instruments ICEMI’2009 A Built-in Self-test Design with Low Power Consumption Based on GeneticAlgorithm Enmin Tan Li Wang School of Electronic Engineering, Guilin University of Electronic Technology,Guilin, 541004, ChinaEmail: tem0135@guet.edu.cn    Abstract   –   A low peak power consumption built-in self-test (BIST) design based on genetic algorithm (GA), which isdenoted by GAITPG, has been proposed in our previous study.This paper presents an improved performance of GAITPG,which also aims at the reduction of the changes between successive test patterns. (m-1) vectors were inserted betweentwo successive n-bit pseudorandom test patterns generated bythe srcinal linear feedback shifted register (LFSR), while mand the element of groups were optimized by GA. Experimental results based on ISCAS’85 benchmark circuits show that thetest pattern generator (TPG) with low power consumption proposed in this paper is efficient, without losing stuck-at fault coverage. Also, a comparison of reduction of power consumption between GAITPG and other scheme (such asinserted TPG (ITPG)) was reported.  Keywords    –  low power consumption design, GA, BIST, TPG, LFSR, weighted switching activity (WSA)    . INTRODUCTIONApproaches on power consumption reduction during built-in self-test (BIST) have appeared. Reference [1] hasa brief overview. A method of them, which was denoted by inserted test pattern generator (ITPG), i.e. the BISTTPG proposed in [1], was based on a linear feedback shifted register (LFSR), leading to pseudosingle-input-change test set to reduce the number of weighted switching activity (WSA) at inputs of thecircuit under test (CUT), as shown in figure 1. Fig. 1. Structure of ITPG. For an n -bit cycle shifted register (CSR), only after  performing one cycle (which equals 2 n CLK cycles) andreturning to all-zero state can the LFSR generate the next pattern. That is to say, the outputs of LFSR maintaincurrent value during the cycle of CSR, at the same time,the n -bit outputs of LFSR perform XOR operation withthe n -bit outputs of CSR one by one, to produce thevectors inserted in two successive patterns from theLFSR. Although the pattern and succedent insertedvectors are correlative, the next pattern generated byLFSR is random, leading to a pseudosingle-input-change test set, which reduce the peak  power consumption ineffectively.A low peak power consumption BIST TPG based ongenetic algorithm (GA), which is denoted by GAITPG,has been proposed in reference [2]. It aimed at thereduction of the changes between successive test patternsand adopts the test-per-clock structure. As shown infigure 2. Fig. 2. Structure of GAITPG. This paper presents an improved performance of GAITPG, followed by a compare of reduction of power consumption with other low power BIST TPG design, asindicated by figure 1..  OPTIMIZING PROCESS BASED ON GAAs showed in reference [2], ( m -1) vectors are inserted between two successive n -bit pseudorandom test patternsgenerated by the srcinal LFSR, and moreover thetransition density of test patterns is lowered availably. Inorder to minimize the power consumption, m and theelement of a group are needed to be optimized by GA, asdescribed in figure 3.The evolutionary process includes roulette selection,one-point crossover, mutations and inversions. By 2-526  _____________________________  978-1-4244-3864-8/09/$25.00 ©2009 IEEE  The Ninth International Conference on Electronic Measurement & Instruments ICEMI’2009calculating and modifying in this paper, mutation probability was set to 0.05, and crossover probability wasset to 0.8. Optimized individuals obtained from someISCAS’85 benchmark circuits are shown in table 1. Fig. 3. Procedure flow chart of GA. For example, the input ports number  n of circuit C432is 36, while the inserted vectors number  V  is 18. After setting a seed f101bb288 to the LFSR, the optimizedindividual calculated by GA is110111111010100000011111110000000001, whichmeans the optimized groups of input ports for low power consumption are 1, 2, 3~4, 5, 6, 7, 8, 9, 10 ~ 11, 12 ~ 13,14 ~ 20, 21, 22, 23, 24, 25, 26, 27 ~ 36..  EXPERIMENT RESULTFirstly C  codes were used to perform the simulationsone by one on the srcinal LFSR, the inserted TPG (asdescribed in figure 1) and the GAITPG, and experimentswere performed on some ISCAS’85 benchmark circuits.The goal of the experiments is first to make sure that thestuck-at fault coverage keeps the same when the testlength of the GAITPG is the same with the srcinal LFSR,and next to measure the total power, the average power and the peak power savings that the GAITPG allows toobtain on the CUT by calculating the WSA , the WSAa andthe WSAp reduction.  A. Simulation on stuck-at fault coverage The stuck-at fault coverage calculations were performed with a concurrent fault simulator   Faultsim of our group. Firstly, the foundational data of someISCAS’85 benchmark circuits are listed in table 2.Then, for example, according to the input portsnumber of table 2, the selected primitive polynomial of LFSR for C432 circuit was 36: 25, 0, by which the VC   development tools schemed out a 36-stage LFSR togenerate test patterns. At last,  Faultsim was used to perform fault simulation and analysis one by one on thesrcinal LFSR and the GAITPG. The results wereindicated respectively in figure 4 and 5. Table 1. Optimized individual by GA.  circuits optimized individualC432110111111010100000011111110000000001C49901010101100101011001101100010000011011111C8800011101111110100111101100000010001100010101111000100011001010C135500011101011111100101010100010011110101100C1908101000011100110010101111110010011C354001111011100011010110011000100001011011001001011010C628810011101000110011011100010011110 Table 2. Foundational data of some circuits. circuitsinput portsnumber output portsnumber gatesnumber faultsnumber C432 36 7 160 524C499 41 32 202 758C880 60 26 383 942C135541 32 546 1574C190833 25 880 1879C354050 22 1669 3228C628832 32 2416 7744Furthermore, a comparison of the stuck-at faultcoverage can be made between the srcinal LFSR and theGAITPG, under the condition that their test length isequal, as shown in table 3. For most of the ISCAS’85 benchmark circuits, both stuck-at fault coverage obtained by the two schemes are very similar.  B. Simulation on power consumption Analogically, C  codes were used to simulate theaforementioned test generation process, which includesthe srcinal LFSR, the inserted TPG shown in figure 1and the GAITPG. Then test set were obtained andapplied to the CUT: some ISCAS’85 benchmark circuits. 2-527  The Ninth International Conference on Electronic Measurement & Instruments ICEMI’2009 Fig. 4. Fault simulation on srcinal LFSR.  Fig. 5. Fault simulation on GAITPG. In the experiment, WSA was used to evaluate theenergy/power consumption of the circuit [4] . That is tosay, as defined in reference [4], WSA is usually used for evaluating total power consumption, while WSAa for average power consumption and WSAp for peak power consumption.With the same test length, a comparison of the WSA ,the WSAa and the WSAp can be made between theGAITPG and the ITPG, as reported in table 4. Asmentioned above, the test length and LFSR parameterswere adopted from table 2 and 3, while the WSA wascounted under the zero-delay model.Table 4 shows that the WSA and the WSAa reductionobtained by GAITPG are similar to that by the insertedTPG, while the WSAp reduction obtained by GAITPGare much higher than that by the ITPG, as farther described in figure 6..  CONCLUSIONAs showed in table 4 and figure 6, GAITPG canhighly reduce the WSA, the WSAa and the WSAp duringBIST application, that is, all the total power/energy, theaverage power and the peak power consumption arehighly reduced. Experimental results based on ISCAS’85 benchmark circuits show that about 26% to 64%reductions in the number of the WSAp are attained,additionally, approximate 50% to 90% reductions of theWSA and the WSAa achieved, without losing thestuck-at fault coverage. Table 3. Simulation result of fault coverage. circu-its primi-tive polyn-omialLFSR seeds [1]testlengthstuck-at faultcoverage (FC)%srcinalLFSR GAITPGC43236  25  0f101bb2882000 99.237 98.885C49941  38  0800000151011600 98.813 98.813C88060  1  016a337634d00a1310000 99.894 98.832C135541  3  0aaaaaaaaaa14000 99.492 99.492C190833  20  044bd2a4 b02000 97.339 94.201C354050  49  24  23  0f8118141811724000 95.741 94.341C628832  31  5  4  0aaaaaaaa2000 99.561 99.561  Table 4. Comparison of power consumption between ITPG andGAITPG. circuits ITPG GAITPG WSA WSAaWSAp   WSA   WSAaWSAp C432 3220316 173 24238 13 136C499 9119914 169 83970 11 107C880 19940319 362 136005 13 193C135536722191 521 238958 59 199C1908258069129728 140033 87 422C35404413241101283 309515 75 839C628816917858452591 914455 8151830 A comparison of reduction of power consumption between GAITPG and ITPG was reported, todemonstrate that GAITPG is much more efficient in thereduction of peak power consumption. 2-528  The Ninth International Conference on Electronic Measurement & Instruments ICEMI’2009 Fig. 6 Peak power consumption reduction rate between GAITPGand ITPG ACKNOWLEDGMENTThis paper was supported by the Natural ScienceFoundation of China (No. 60861003). Specially, theauthors wish to thank Jia Lei for the opportunity he gavethe authors to present this work at the CAT laboratory of Guilin University of Electronic Technology, XuelongYan for many discussions on algorithms, and theanonymous reviewers for their valuable comments.This work was supported by the Natural ScienceFoundation of China (NSFC) under grant No. 60861003.REFERENCES [1] R. H. He, X. W. Li, and Y. Z. Gong, “A low power BIST TPGdesign”. Proceedings of the 5th international conference on ASIC,2003. 1136-1139, vol. 2.[2] E. M. Tan, S. D. Song, and W. K. Shi, “Power Reduction in BISTDesign Based on Genetic Algorithm and Vector-Inserted TPG”.Proceedings of 2007 8 th International Conference on ElectronicMeasurement & Instruments. Xi’an,2007,Vol.  . 4-533-537.[3] X. D. Zhang, W. L. Shan, and K. Roy. “Low-power weightedrandom pattern testing”.  IEEE Transactions on CAD of ICs and Systems , 2000, 19(11): 1389-1398.[4] N. Ahmed, M. H. Tehranipour, and M. Nourani, “Low power  pattern generation for BIST architecture”. Proc. of the 2004International Symposium on Circuits and Systems, (ISCAS '04), pp. II - 689-92 Vol.2, May 23-26,2004.[5] P. Girard. “Survey of Low-Power testing of VLSI Circuit”.  IEEE  Design & Test of Computers , 2002, 19(3): 82-92.[6] M. L. Bushnell, and V. D. Agrawal, “Essentials of ElectronicTesting for Digital, Memory & Mixed-Signal VLSI Circuits”,Publishing House of Electronics Industry, pp.369-395, 2005.   2-529
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