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A Fully Digital Approach in Sensing and Processing Photoplethysmographic Signal

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A fully digital sensor-actuator has been developed for photoplethysmographic (PPG) measurements. Instead of classical sensor it uses standard light emitting diodes (LEDs) for both light emitting and detecting. Time-duration based conversion protocol
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  A fully digital approach in sensing and processing  photoplethysmographic signal Radovan Stojanovi ć   Faculty of Electrical Engineering, University of Montenegro Podgorica, Montenegro e-mail: stox@ac.me  Dejan Karadagli ć   Department of Electrical and Electronics Engineering University of Manchester Manchester, UK e-mail: dejan.karadaglic@manchester.ac.uk   Bogdan Ašanin Scholl of Medicine University of Montenegro Podgorica, Montenegro e-mail: asanin@cg.yu   Abstract   —A fully digital sensor-actuator has been developed for photoplethysmographic (PPG) measurements. Instead of classical sensor it uses standard light emitting diodes (LEDs) for both light emitting and detecting. Time-duration based conversion protocol is implemented by a field programmable gate array (FPGA) avoiding the need for analog amplifiers and precision analogue to digital converters (ADCs). The basic sensing configuration, presented here, consists of a pair of LEDs directly connected to two FPGA’s I/O pins and is capable of detecting the PPG signal from a finger or a toe. The better spectral sensitivity, increased and adjustable resolution, reduced noise, lower cost and dimensions are confirmed advantages. In this paper we introduce a sensing principle in conjunction with pulse-based measurement technique, signal filtering and data communication implemented in a single FPGA chip. The approach in general, as well as the prototype in particular, where evaluated through both qualitative and quantitative experiments.  Keywords; PPG, measurement, microcontroller, sensor I.   I  NTRODUCTION Photoplethymysography (PPG) is a non-invasive method for the detection of cardiovascular pulse waves propagated around the human body. It is based on the determination of optical properties of vascular tissue using a probe, which consists of an LED-photodiode configuration [1], [2]. The LEDs run as light emitters and the photodiodes (usually p-i-n, PINs) as light detectors (PDs). The probe is placed on the  periphery of body, most commonly on a finger or a toe and can operate in reflectance or transmittance mode. The emitted light is reflected, absorbed or scattered by the blood and tissues. The intensity of the light reaching the PD is measured and the variations, caused by blood volume changes, are amplified, filtered and recorded as a voltage signal. This signal is extremely small, suppressed by noise and in addition to the PD,  precise analog amplifiers, high order filters and analogue to digital converters are required [3]. These other components not only increase system complexity and cost, but also its size and  power dissipation. PIN detectors are not ideal as they are not spectrally selective and indiscriminately detect wide spectrum light ranging from near infrared to UV, what significantly responds to the motion artifacts. Today, numerous miniature, battery powered medical devices tend to be simple, robust and multifunctional. It can be done only if they comprise trivial sensors and highly integrated attenuators in SoC form (Sytem on Chip). Aimed with research results given in [4] and [5] as well as with flexibility and advantages of FPGA design we have developed a PPG sensor requiring only a pair of LEDs and single FPGA device. Using a proposed approach it is possible to obtain and digitalise the PPG signals directly form LED receiver without amplification. Section 2 explains proposed sensing methodology through its theoretical model and experimental verification. FPGA architecture for conversion, signal filtering and data communication is described in Section 3, while Section 4 elaborates preliminary testing results with emphasis on using such device in detection and analyse of PPG signal.. II.   S ENSING A PPROACH  The proposed sensing technique is fully digital. Based on the voltage to pulse duration conversion, it eliminates a need for precise analogue amplifiers, filters and ADCs. Fig. 1  presents the simple PPG signal detector, which uses two standard LEDs, usually infrared (IRs), connected to two FPGA’s pins. The emitter (LED1) is driven directly from output pin P1, while the receiver (LED2) is connected to pin P2, which can operate in output or input mode depending on I/O DIR state (0=”out”, 1=”in”). 978-1-4244-4134-1/09/$25.00 ©2009 IEEE  Fig. 2 illustrates the sensing principle, electrical models and algorithmic steps necessary to understand circuit operation. During “STEP1” the emitter diode is switched on and the receiver diode is charged to the voltage V DD  (+5V or +3.3V) almost immediately (within 100-200 μ s). This charge is held by the sum of the inherent capacitances of the diode and I/O pin itself, C r  =C rLED +C rpin . Typically C rLED =10-15pF and C rpin =3-5pF. Pin P2 is then switched into the high-impedance (Hi-Z) state (approximately 10 15    Ώ ), “STEP2”. This decreases the leakage current i L  through the pin P2 down to 0.002pA which is insignificant compared to the typical photocurrent of 50pA through the diode itself, when the emitting LED1 is off. As see, under reverse bias conditions, a simple model for the LED2 is a capacitor Cr in parallel with a current source i R  ( Φ  , ), which models the optically induced photocurrent for incoming light intensity Φ  . Figure 1. FPGA-based PPG sensor. The process of Cr discharging, assuming that i R  ( Φ  ) has constant value, can be expressed as: ( ) t C iVccdt t i C V t v t o r  R Rr CC  P   ∫  Φ−=−= )(1)( 2   (1) As seen, the v P2 (t) linearly decreases with time t to zero. Experimentally recorded traces of this voltage follows (1), Fig. 3, whereby Φ  1 < Φ  2 < Φ  3 . Voltage v P2 (t) is continually polled through its digital equivalent, the logic state of the input pin P1 (see Fig. 1) using symbolic routines, “STEP2”, based on a binary timer-counter, until the logic “0” threshold V TR   is reached. For Complementary Metal Oxide Semiconductor (CMOS) FPGA devices, the V TR   varies with mV V   DD 1002 ± . Decay time (Td) is  proportional to the amount of light detected, hence it measures the diode photocurrent i R  ( Φ  ): ( )( ) tclk tclk TRCC  Rr d   f   N T  N V V  iC msT  1][  ==−Φ=   (2) where N represents the timer’s counts and ftclk the timer clock frequency. As shown, Td decreases when the amount of received light increases and vice versa. For light intensities Φ  1 , Φ  2 and Φ  3 , N corresponds to count values N 1 , N 2  and N 3 , Fig. 3. Figure 2. Digital sensing protocol. The resolution of measurable decay time Δ Td can be adjusted by ftclk¸ whereby the counter bit length ( l  ) needs to be enough to escape overflow, 2 l  -1<Nmax. By measuring the decay times with the emitter LED on and off alternately, we can perform a differential measurement and compensate for the effects of ambient lighting. Usually, ftclk has been extracted from main clock fclk using frequency divider with selectable  prescale factor Np, f  tclk  = f  clk  /Np, Np=2,4,8…. This gives a  possibility to adjust Td resolution by Np: clk  pd   f   N  N msT   ∆=∆ ][   (3) Thus, the maximal resolution is obtained for Np,=1 and minimal step of the counter Δ  N=1. As example, for fclk =200MHz achieves value of 5ns.  In the case of human finger or toe, due to the configuration of light paths, the photo current is proportional to the volume and the fluctuations of blood inside the finger or lobe. It is in the range of 10 -12A (1pA) in total darkness to about 10 -6A  (1 μ A) under maximal reflectance. As example, for maximal reflectance and C r  =15pF, V TR  =V DD /2, Td peaks to 0.150ms  behind resolution of 2.2ns for 16bits and 8ps for 24bits counter. Figure 3. The processes of LED discharging. III.   FPGA  IMPLEMENTATION OF THE SENSING AND PROCESSING CIRCUITS  Previously described decay time meter could be implemented by using general-purpose microcontrollers (MCs) or Programmable Logic Devices (PLDs). The designers often choose MCs because they traditionally offer better on-chip  peripherals, such as timers, ADCs, universal asynchronous receivers/transmitters (UARTs), pulse width modulation (PWM) and other integrated I/O for multiple, asynchronous tasks. Because they are of general purpose, MCs are more flexible and less specialized, which usually makes them easier for understanding and programming. Using MCs in this case is easier and more economical way, but there are several restrictions such as Von Neumann architecture, limited numbers of fixed length timers/counters (usually 2 with 16bits), clock frequency up to 32MHz, low Digital Signal Processing (DSP) capabilities, insufficient parallelism and several software layers. Unlike processors, FPGAs use dedicated hardware for  processing logic and do not have an operating system (OS). Since they are truly parallel in nature, different processing operations do not have to compete for the same resources. FPGAs and processors also differ in compilation. When an application for an FPGA device is compiled, the result is a highly optimized silicon implementation that provides parallel  processing with the performance and reliability benefits of dedicated hardware circuitry. Because there is no OS on the FPGA, the code is implemented in a way that ensures maximum performance and reliability. In contrast to first families, nowadays FPGAs do not only offer a lot of logic base cells, but also huge register blocks and memory areas and  powerful processor cores. Their speed may achieve 500MHz. We got experience in both MC’s and FPGA’s PPG sensors. In this paper we point to the FPGA technology. The architecture we propose consists of several functional units, Fig. 4. PPG meter excites emitter diode LED1 and measures the decay time Td by tracking voltage on LED2. The digital equivalent of Td, stored in the timer counter, is sent to the UART directly or via Digital Filter section, depending on the MUX state, on or off. In order to optimize filter design, we investigated two configurations: Mean filter and finite impulse response (FIR) filter. The 16th order integer arithmetic mean filter has been created as: { } )1(...)2()1()( 1)(  +−++−+−+=  ni xi xi xi x ni y   (4) The symmetric coefficient FIR filter is realized with border frequency of 10Hz, and whose time domain transfer function is given by: )1(...)2()1()()( 210  +−++−+−+=  ni xai xai xai xai y n   (5) The coefficients a(i) are multiplied and rounded in order to  be pre-scaled in integer arithmetic. CLK_DIV determines timer frequency ftclk for different prescaled factors. UART sends the srcinal or filtered data to the host computer with selectable speeds. All functional modules are realized in the form of Very High Speed Integrated Circuit Hardware Description Language (VHDL code with generic arguments (data widths, filter order, sampling frequency, communication speed, pipeline and so on). Overall design is carried out in Altera Quartus II development environment. Figure 4. FPGA architecture, digital modules. IV.   P RELIMINARY RESULTS  The proposed PPG sensor-actuator was tested in 2LEDs configuration. The sensing probe comprises an IR-IR, 5mm LED combination (910nm wavelength). The signal is collected in reflectance mode from a finger. As a target chip, an FPGA  from Altera Cyclone (EP1C6Q240C8) series has been chosen. The inherent capacitance of its I/O pin is about 4pF. The chip was supplied by 3.3V, running at 48MHz, allowing maximal resolution of 20ns, towards temperature of 30oC. The signals are sampled at 200Hz and sent via RS232 interface at 19200bps to host computer, where a MATLAB-based virtual instrument is designed for data importing, post-processing and displaying. The instrument allows several real-time functions such us filtering, Fast Fourier Transform (FFT), time-frequency analysis (TF) and statistics, all in real time. The prototype is evaluated through both qualitative and quantitative experiments. Fig. 5a) and c) shows the srcinal time domain PPG signal obtained by IR-IR combination from 23 years female and male students. The signal from Fig. 5 a) is  processed by 16th order FIR filter with cut-off frequency of 10Hz, Fig. 5 b). The signal from Fig. 5 c) is filtered by 16th order Mean filter, Fig. 5 d). As shown, the both filters are effective and can be used to eliminate 50Hz flicker. Figure 5. Original PPG signals and equivalents after implementation of different filtering. Fig. 6 illustrates the occupancy of silicon resources on target devices for different combinations of built in components. The basic configuration consists of PPG meter and UART occupies only 4.6% of hardware resources in case of EP1C6Q240C8 chip. Hardware requirements grow as the filters sections are added to the basic configuration. As example, FIR filter is more demanding than Mean one, increasing resources from 13.3% to 28.4% (more than twice). Obviously, more optimal and efficient structure is PPG meter + Mean filter + UART. In this case a single FPGA chip EP1C6Q240C8 can integrate 8 parallel PPG channels. In future work the authors will use the proposed principle for various purposes: (i) heart rate monitor, (ii) SpO 2 meter, (iii) multichanel parallel monitoring of PPG signal (ear, finger and forehead) and (iv) noninvasive cuffless measurement of blood  pressure (BP) by Pulse Transmit Time (PTT). The existing configuration will be upgraded with modules like: peak detector, FFT and SpO 2  calculator. Figure 6. Resource occupation for different configurations. V.   C ONCLUSION  We have demonstrated fully digital PPG sensor. Instead of classical one it uses standard LEDs for both light emitting and detecting. Time-duration based conversion protocol is implemented by FPGA avoiding the need for analog amplifiers and precision analogue to digital converters. The proposed sensing technique results in good spectral sensitivity, excellent signal to noise ratio, low power consumption, flexibility, reconfigurability and miniaturization. FPGA chip is used as a sensor, DSP and communication module. The developed core should be integrated in various systems on chip or microprocessors. A CKNOWLEDGMENT The authors are grateful to Ministry of Education and Science of Montenegro for supporting this project. R  EFERENCES   [1]   J. Allen, “Photoplethysmography and its application in clinical  physiological measurement”, Physiological Measurements, 28 No 3, 2007, R1-R39. [2]   S. Rhee, B.H. Yang and H.H Asada, “Artifact-Resistant Power-Efficient Design of Finger-Ring Plethysmographic Sensors”, IEEE Transactions on Biomedical Engineering, 48 7, 2001, pp. 795- 805. [3]   V. Jaiganesh and M. Sankaradass, “PC based heart rate monitor implemented in XILINX FPGA and analysing the heart rate”, Proceedings of CCS 2005, Vojin G. Oklobdzija (Ed.), pp. 319-323. [4]   K.T. Lau, S. Baldwin, R.L. Shepherd, P.H. Dietz, W.S. Yerazunis and D. Diamond, “Novel Fused-LEDs Devices as Optical Sensors for Colorimetric Analysis”, Talanta, 63 1, 2004, pp. 167-173. [5]   K.T. Lau, S. Baldwin, R.L. Shepherd, P.H. Dietz, W.S. Yerazunis and D. Diamond, “Novel Fused-LEDs Devices as Optical Sensors for Colorimetric Analysis”, Talanta, 63 1, 2004, pp. 167-173. [6]   E. Miyazaki, S . Itami and T. Araki, “Using a light-emitting diode as a high-speed, wavelength selective detector”, Review of scientific instruments, 69 11, 1998, pp. 547-588. [7]   R. Stojanovi ć  and D. Karadagli ć , “Single LED Takes On Both Light-Emitting And Detecting Duties”, Electronic Design, Vol. 55, No. 16, 2007, pp. 53-54.
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