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A New Leakage Reduction Method for Ultra Low Power VLSI Design for Portable Devices.pdf

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     Abstract  -- Portable electronic devices are integral components in our quotidian life. These devices require charging after a certain amount of usage time. Most of the time during discharging cycle, they remain idle or inactive. If these devices are not in active use, why does the battery discharge? The answer is leakage power consumption. At present the power density in CMOS integrated circuits has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. With downward scaling of technology, static power consumption is becoming more dominant. It is challenging for the circuit designers to balance both scaling and low static power demands. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using stacked sleep transistor without being penalized in power delay product requirement and circuit performance.  Index Terms  —  Low Power VLSI design, Sleep transistor, Stack effect, State saving technique, Variable body biasing. I. I  NTRODUCTION  OWER dissipation consists of dynamic and static components in CMOS digital circuits. As the feature size  becomes smaller for achieving high density and higher  performance, shorter channel lengths result in increased subthreshold leakage current through a transistor when it is off. Another reason for low threshold voltage resulting in increased subthreshold leakage current is that, transistors cannot be turned off completely. For these reasons, static  power consumption, i.e., leakage power dissipation, has  become a significant portion of total power consumption for current and future silicon technologies. There are several VLSI techniques to reduce leakage power. Each technique  provides disparate ways to reduce leakage power, but disadvantages of each technique circumscribe the application of each of them. We propose a new approach, thus providing a new choice to low power VLSI designers. Asif Jahangir Chowdhury is with the Department of Electrical and Electronics Engineering, Bangladesh University of Engineering and Technology, Dhaka, Bangladesh (e-mail: Md. Shahriar Rizwan is with the Department of Electrical and Electronics Engineering, Bangladesh University of Engineering and Technology, Dhaka, Bangladesh (e-mail: Shahriar Jalal Nibir is with the Department of Electrical and Electronics Engineering, Bangladesh University of Engineering and Technology, Dhaka, Bangladesh. (e-mail: Md. Rifat Alam Siddique is with the Department of Electrical and Electronics Engineering, Bangladesh University of Engineering and Technology, Dhaka, Bangladesh (e-mail: II. P REVIOUS M ETHODS  Previously proposed circuit level approaches for subthreshold leakage power reduction are discussed here:  A. Sleep Transistor Technique The widely used technique is the sleep approach [1]-[2] (Fig. 1). In the sleep approach, an additional “sleep” PMOS transistor is placed between VDD and the pull-up network and an additional “sleep” NMOS transistor is placed betwe en the  pull-down network and ground. These sleep transistors turn off the circuit by cutting off the power rails in the sleep mode. By cutting off the power source, this technique can reduce leakage power effectively. However, the technique results in destruction of state plus a floating output voltage in sleep mode.  B. Sleepy Stack Technique When stack effect is smartly mixed with the sleep transistor technique the sleepy stack technique is developed [3]-[4] (Fig. 2). The sleepy stack technique divides existing transistors into two half length transistors utilizing the stack effect. Then sleep transistors are connected in parallel to one of the divided transistors. During sleep mode, sleep transistors are turned off and stacked transistors suppress leakage current while saving state. Power delay product penalty is a significant matter for this approach since every transistor is replaced by three transistors. Fig. 1. Sleep Transistor Fig. 2. Forced Stack C. Sleepy Keeper Technique Sleepy keeper utilizes leakage feedback technique [5]-[6] (Fig. 3). In this technique, a PMOS transistor is placed in  parallel to the sleep transistor (S) and a NMOS transistor is  placed in parallel to the sleep transistor (S'). The two transistors are driven by the output of the inverter. During sleep mode, sleep transistors are turned off and one of the A New Leakage Reduction Method for Ultra Low Power VLSI Design for Portable Devices Asif Jahangir Chowdhury, Student Member, IEEE  , Md. Shahriar Rizwan, Student Member, IEEE  , Shahriar Jalal Nibir and Md. Rifat Alam Siddique P 2012 2nd International Conference on Power, Control and Embedded Systems978-1-4673-1049-9/12/$31.00 ©2012 IEEE   Fig. 3. Sleepy Keeper transistors in parallel to the sleep transistors keep the connection with the appropriate power rail.  D. Dual Sleep Technique Dual sleep technique [7] (Fig. 4) uses the advantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the dual sleep portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.  E. Dual Stack Technique In dual stack technique [8] (Fig. 5), 2 PMOS in the pull-down network and 2 NMOS in the pull-up network are used. The advantage is that NMOS degrades the high logic level while PMOS degrades the low logic level. Compared to previous techniques it requires greater power delay product. The delay is also increased. Fig. 4. Dual Sleep Fig. 5. Dual Stack III. P ROPOSED T ECHNIQUE  Subthreshold leakage can be reduced by stacking transistors, i.e., taking advantage of the so- called “stack effect”  [9]. The stack effect occurs when two or more stacked transistors are turned off together; the result is reduced leakage  power consumption. Let us explain an important stack effect leakage reduction model. The model we explain here is based on the leakage models in [9] and [10]. For a turned off single transistor leakage current (  I   sub0 ) can be expressed as follows: )1(  /)(0 00000       V V V V V V  nV  sub dsds sbth gs e Ae I       (1) )( 0  dd th  V V nV   Ae         (2)   Where, 8.12 )(  eV  LW C  eff  oxo       ; n  is the subthreshold swing coefficient, and V  θ    is the thermal voltage.  V   gs0 , V  th0 , V   sb0  and V  ds0  are the gate-to-source voltage, the zero-bias threshold voltage, the base-to-source voltage and the drain-to-source voltage, respectively ,   γ   is the body-bias effect coefficient, and η  is the Drain Induced Barrier Lowering (DIBL) coefficient ,    µ  is zero-bias mobility, C  ox   is the gate-oxide capacitance, W   is the width of the transistor, and  L eff   is the effective channel length [9]. Let us assume that the two stacked transistors (M1 and M2) in Fig. 6 are turned off. We also assume that the transistor width of each of M1 and M2 is the same as the transistor width of M0 ( W   M0  = W   M1  = W   M2 ). Two leakage currents  I   sub1  of the transistor M1 and  I   sub2  of the transistor M2 can be expressed as follows: )1(  /)(11 11101       V V V V V V  nV  sub dsds sbth gs e Ae I       (3) )((1 0 ,  xdd  xth x  V V V V V  nV  sub  Ae I or           (4) )1(  /)(2 22202       V V V V V V  nV  sub dsds sbth gs e Ae I       (5) )1(,  /)(2 0      V V V V nV  sub  x xth e Ae I or       (6) Where V   x  is the voltage at the node between  M1  and  M2 , and we assume . Now consider leakage current reduction between  I   sub0  and I  sub1 (=I  sub2 ). The reduction factor X can be expressed as follows: Fig. 6. (a) A single transistor (left) and (b) stacked transistors (right) )1()((1)(110 00                nV V V V V V V  nV V V nV  sub sub  x xdd  xth x dd th e Ae Ae I  I   (7) in (7) can be derived by letting  I   sub1  =  I   sub2  and by solving (8).        V V V V nV   x xdd  ee  /)21(( 1 1     (8) If all the parameters are known, we can calculate stack effect leakage power reduction using (7) and (8). As an example, we consider leakage model parameter values targeting 0.5µ technology in Table I obtained from [9]. TABLE I L EAKAGE M ODEL P ARAMETER (0.5  µ   T ECH ) Parameter Value V dd  1V V th  0.2V n (subthreshold slope coefficient) 1.5   (DIBL coefficient) 0.05V/V   (body-bias effect coefficient) 0.24V/V    From (8), we calculate V   x = 0.0443V, and from (7), we obtain leakage reduction factor X =4.188. From this example we can realize that stacking two transistors can effectively enervate leakage current. We know that static power is the  product of voltage and leakage current. As leakage current reduces due to stack effect, static power also reduces consequently. IV. S IMULATION M ETHODOLOGY  The stacked sleep technique is compared with four   of the techniques explained earlier namely; sleep transistor, sleepy stack, dual sleep and dual stack. Thus, five  design approaches are compared in terms of power consumption (dynamic and static), delay and power delay product. To show that the stacked sleep technique approach is applicable to general logic design a chain of 4 inverters (Fig. 7) is chosen. HSPICE [11] was used for simulation purpose to estimate delay and power consumption. All considered techniques are evaluated for  performance by using a single, low- V  th  for all transistors in chain of 4 inverters and high- V  th  in the sleep transistors. Applying high-  V  th  reduces static power. For the dual V  th  technique, high-  V  th  is used for leakage reduction transistors and low-  V  th  is used for the other transistors. The high-  V  th  is set to have 0.1V higher   V  th  than the V  th  of a normal transistor (low-  V  th ).The inverter chain uses four inverters each with W/L=6 for PMOS and W/L=3 for NMOS for the base case. Sleep transistors used in the pull-up and pull-down networks of the base case inverter chain have W/L=6 and W/L=3. The stacked sleep transistor approach transistor size is shown in Fig. 7.   The chosen technologies are BSIM4 PTM Model [12] and their supply voltages are given in Table II. TABLE II   C HOSEN TECHNOLOGY AND V DD VALUE  130 nm   90 nm   65 nm   45 nm   32nm   1.3 V   1.2 V   1.1 V   1.0 V   0.9 V   Fig 7. Proposed Stacked Sleep Approach V. S IMULATION R  ESULTS  Static power consumption, dynamic power consumption ,   propagation delay  and power delay product  for five design approaches, which are sleep, sleepy stack, dual sleep, dual stack and variable body biasing approach were measured. Fig. 8, Fig. 9, Fig. 10 and Fig. 11  exhibit, static power consumption, dynamic power consumption, propagation delay comparison and power delay product for a chain of four inverters, respectively. Fig 8. Static Power Comparison   Fig 9. Dynamic Power Comparison Fig 10. Delay Comparison Fig 11. Power Delay Product Comparison      The comparisons of stacked sleep technique using 65 nm technology with the existing methods for a chain of four inverters are summarized in Table III .   Here „+‟ denotes improved and „ - ‟ denote s degraded performance.  TABLE III C OMPARISON W ITH P REVIOUS T ECHNIQUES (65   nm  TECH ) Different Methods Static  power Dynamic  power Delay Power delay  product Sleep transistor +71.80 +69.12 -307.38 -25.8333 sleepy stack +98.97 +59.49 -138.37 +3.514377 dual sleep +98.99 +69.41 -285.05 -17.5097 dual stack +98.63 +29.40 -165.38 -86.4198 From the comparison we can see that the stacked sleep transistor offers very good static and dynamic power reduction. But it suffers from delay. Nevertheless, in applications where delay can be compromised for low power, stacked sleep approach can be very useful. VI. C ONCLUSION  An efficient method for reducing leakage power in VLSI design is presented in this paper. We applied Stacked Sleep Transistor technique to a chain of four inverter circuit. Then we compared static power, dynamic power, propagation delay and power delay product of the circuit with previously  proposed methods. The Stacked sleep transistor approach shows improved results in terms of static and dynamic power. It gives the CMOS circuit designers another option in designing integrated circuits more efficiently. VII. R  EFERENCES   [1]   S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada, “1 -V Power Supply High-speed Digital Circuit Technology with Multithreshold- Voltage CMOS,” IEEE Journal of Solis -State Circuits, Vol. 30, No. 8, pp. 847-854, August 1995. [2]   M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, “Gated -Vdd: A Circuit Technique to Reduce Leakage in Deep-submicron C ache Memories,” in  Proc.   2000  International Symposium on Low Power Electronics and Design, pp. 90-95, July 2000. [3]   J.C. Park, V. J. Mooney III and P. Pfeiffenberger, “Sleepy Stack Reduction of L eakage Power,” in  Proc. 2004  International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 148-158, September 2004. [4]   J. Park, “Sleepy Stack: a New Approach to Low Power VLSI and Memory,” Ph.D. Dissertation, School of Electrical and Computer   Engineering, Georgia Institute of Technology, 2005. [Online] available [5]   J. Kao and A. Chandrakasan, MTCMOS sequential circuits,” in  Proc. 2001  European Solid-State Circuits Conf., pp 332-335, September 2001. [6]   Se Hun Kim, V. J. Mooney, “Sleepy Keeper: a New Approach to Low -leakage Power VLSI Design,” in  Proc. 2006 IFIP International Conference on Very Large Scale Integration, pp 367-372, October, 2006. [7]    N. Karmakar, et al., “A novel dual sleep approach to low leakage and area efficient VLSI design”  in  Proc, 2009  IEEE Regional Symposium on Micro and Nano Electronics(RSM2009), Kota Bharu, Malaysia, pp. 409-414, August 10-12, 2009. [8]   M. S. Islam, et al., “Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI Design”  in  Proc. ICECE2010 , Dhaka, Bangladesh. pp. 89-92, December 18-20, 2010. [9]   Johnson, M. C., Somasekhar, D., And Roy, K., “Models and Algorithms for Bounds on Leakage in CMOS Circuits,” IEEE Transactions on Computer Aided Design on Integrated Circuits and Systems, vol.18, no.6, pp.714  –  725, June 1999. [10]    Narendra, S., De, V., Borkar, S., Antoniadis, D. A., And Chandrakasan, A.P., “Full -Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub- 0.18um CMOS,” IEEE Journal of Solid -State Circuits, vol.39, no.2, pp.501  –  510, February 2004 [11]   Synopsys Inc. [Online]. Available [12]   Berkeley Predictive Technology Model. [Online]. Available
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