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A new voltage mode quadrature oscillator using grounded capacitors An application of CDBA.pdf

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  Full Length Article A new voltage mode quadrature oscillator using grounded capacitors: Anapplication of CDBA Tajinder Singh Arora ⇑ , Soumya Gupta Maharaja Surajmal Institute of Technology, Janakpuri, New-Delhi, India a r t i c l e i n f o  Article history: Received 29 October 2017Revised 10 January 2018Accepted 13 January 2018Available online 13 February 2018 Keywords: Single-resistance-controlled oscillatorQuadrature outputsCurrent differencing buffered amplifiersVoltage mode oscillators a b s t r a c t The paper realizes a single-resistance-controlled oscillator employing current differencing bufferedamplifiers as active devices, and virtually grounded resistors and grounded capacitors as passive compo-nents. Operating in voltage mode, the designed circuit is capable of generating quadrature outputs alongwith an unambiguous control of oscillating frequency and condition of oscillation. Initially, practicalityand feasibility of the design has been justified by the results obtained using PSPICE simulation software.Simulation results include time response and frequency response outputs generated by using the com-mercially available I.C. of CFOA, i.e. AD844, as well as by using the CMOS structure of active deviceemployed. Later, hardware experimentation of the design has been included, for which AD844 along withstandard components have been employed. Validating results have been obtained in both the cases.   2018 Karabuk University. Publishing services by Elsevier B.V. ThisisanopenaccessarticleundertheCCBY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). 1. Introduction Analog signal processing encounters a wide use of filters andoscillators [1,2,3]. Use of various different active devices such asCurrent Feedback Operational Amplifier (CFOA) [4,5], Current Con-veyors (CC) [6,7], Differential Voltage Current Conveyor (DVCC)[8,9], Voltage Differencing Current Conveyor (VDCC) [10,11], Oper- ational Transconductance Amplifiers (OTA) [12,13] etc. in generat-ing these filter or oscillator networks has been frequentlywitnessed in literature. In 1999, a new active building block wasproposed by Acar and Ozoguz [14], which was named as CurrentDifferencing Buffered Amplifier (CDBA). This versatile device hasa wide frequency range and is suitable for both current and voltagemode operations. These features encouraged a widespread use of CDBA in realization of circuits like filters, oscillators, and convert-ers, to name a few [15,16] and also references cited therein.Single-resistance-controlled oscillator (SRCO) refers to a blockthat generates a continuous periodic, oscillating electronic signal,whose frequency of oscillation (F.O.) and condition of oscillation(C.O.) are controllable by a separate individual resistive element.Finding application in telecommunication and instrumentation,quadrature sinusoidal oscillators are the ones which produce out-puts with 90   phase shift. For evaluating the efficiency of SRCOconfigurations several factors are taken into consideration suchas: (a) employment of minimum active and passive components,(b) efficient tunability of F.O. and C.O., (c) working frequency of designed oscillator, (d) easier cascadibility, and (e) efficient inte-grated circuit implementation and so on.Exploring the versatility of device CDBA further, the authorshave devised a network acting as an oscillator and offering the fol-lowing features: (a) two active components, (b) low passive com-ponent count (c) easy tunablility of F.O. and C.O., (d) groundedcapacitors and hence easier IC implementation, (e) high oscillatingfrequency and (f) generation of quadrature outputs. Entirely basedon above mentioned features, an elaborated comparison has beenprovidedinTable1.As per thetable, oneof theworkdoneonCDBA[23] is similar to the presented work. However, other worthy fac-tors which became the basis of comparison are frequency of oscil-lation, number of IC employment and simulation results. Thefrequency of oscillation achieved in designed SRCO is 500 kHzwhereas that achieved in previous work [23] is 15.91 kHz. Also,the simulation results shown there were using AD844 only butsimulations shown in this work is using CMOS and AD844. In sim-ulating the SRCO proposed [23], four AD844 were used but hereonly three have been used. Hence, proposed configuration of thismanuscript has several other advantages when compared to SRCOdesigned previously.According to the literature survey conducted, there are manycircuits available in literature which provide some of the men-tioned features, but no circuit has the capability of supporting allthe features and simulations presented in this work. Hence, there https://doi.org/10.1016/j.jestch.2018.01.0062215-0986/   2018 Karabuk University. Publishing services by Elsevier B.V.This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). ⇑ Corresponding author. E-mail address:  tajarora@msit.in (T.S. Arora).Peer review under responsibility of Karabuk University.Engineering Science and Technology, an International Journal 21 (2018) 43–49 Contents lists available at ScienceDirect Engineering Science and Technology,an International Journal journal homepage: www.elsevier.com/locate/jestch  is a successful bridging of gap between the previous circuits anddesigned circuit, through this manuscript.Divided among various sections, the present section gives theintroduction of analog signal processing, quadrature oscillatorsand comparison between previous work and presented work.While the next section, i.e. Section 2, will introduce the activebuilding block of this manuscript (CDBA). Section 3 contains thedesigned circuit with its ideal analysis. Non-ideal and sensitivityanalysis are stated in Section 4. Occupying Section 5 is the analysis of the configuration with parasitic effects under consideration.Tabulation of THD results is done in Section 6. Verifying the theo-retical analysis, Section 7 contains all the simulation resultsobtained through PSPICE. Experimental results, with circuit designand related theoretical discussion, is presented in Section 8. At last,conclusion is provided in Section 9. The nomenclature used incomplete manuscript is defined in Appendix (A-1), provided atthe end. 2. Current differencing buffered amplifier  CDBA is a two-input two-output terminal device, shown inFig. 1. Amongst the available ports, P and N are low impedanceinput ports whereas Z terminal is high impedance output portand W is low impedance output port.On ignoring the non-idealities of the device employed, the idealcharacteristic equations of CDBA are derived, as given in (1). Thesearebasicallyobtainedbyanalyzingtheidealstructureof thedeviceshown in Fig. 2.Ideal analysis of circuits generated using CDBA as active deviceis done using these equations given below. V  P   ¼  V  N   ¼  0 V  W   ¼  V   Z  I   Z   ¼  I  P    I  N  ð 1 Þ As defined in literature, CDBA can be generated by employingthe commercially available I.C. of CFOA, i.e. AD844 [1], or by using MOSFETswithasuitabletechnology[27].Boththeserealizationsof CDBA are shown in Figs. 3 and 4 respectively.Practically CDBA is characterized by equations given in (2)which are also used during non-ideal analysis of circuits generatedusing CDBA as active building block. V  P   ¼  V  N   ¼  0 V  W   ¼  d V   Z  I   Z   ¼  a I  P     b I  N  ð 2 Þ where a ,  b  and  d  are port transfer ratios of P, N and Z terminalsrespectively.  Table 1 Comparison between previous work and presented work. Reference No. Number of CDBA Number of passive components All grounded Capacitors Independent C.O. and F.O.[17] 2 5 No Yes[18] 2 6 Yes Yes[19] 2 6 Yes Yes[20] 2 6 No Yes[21] 1 5 No Yes[22] 2 8 No No[23] 2 5 Yes YesCircuits 1–4 [24] 2 6 Yes YesCircuits 5–12 [24] 2 6 No Yes[25] 2 5 No Yes[26] 2 5 No YesProposed Circuit 2 5 Yes Yes Fig. 1.  Symbol of CDBA. Fig. 2.  Ideal structure of CDBA obtained by voltage sources and current sources. Fig. 3.  CDBA implementation using AD844. Fig. 4.  CMOS arrangement of employed CDBA [27].44  T.S. Arora, S. Gupta/Engineering Science and Technology, an International Journal 21 (2018) 43–49  3. Proposed circuit The circuit for SRCO has been designed keeping in mind easierand efficient integrated circuit implementation and hence the cir-cuit contains only two capacitors, both grounded in nature, andthree resistors among which two are virtually grounded. UsingonlytwoCDBA,bykeepingF.O.andC.O. independentof eachother,the configuration has been designed, which is given in Fig. 5.Analyzing the circuit shown in Fig. 5 using characteristic equa-tions given in (1), the ideal characteristic equation for oscillator isobtained as stated in (3). For initiating and sustaining the oscilla-tions of constant amplitude in any oscillator network, a conditionhas to be fulfilled which is termed as condition of oscillation. Thefrequency at which these oscillations are obtained is termed as fre-quency of oscillation.Frequency and condition of oscillation are derived as shown in(4) and (5) respectively. s 2   sC  1 1 R 3   1 R 2    þ  1 R 1 R 2 C  1 C  2 ¼  0  ð 3 Þ FO  :  x 0  ¼  ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 R 1 R 2 C  1 C  2 s   ð 4 Þ CO  :  R 3  6 R 2  ð 5 Þ The above derived equations indicatethat F.O. can be controlledfrom virtually grounded resistor  R 1  whereas C.O. can be varied byanother virtually grounded resistor i.e.  R 3 . Hence, the designed cir-cuit is capable of acting as a single-resistance-controlled oscillator. 4. Non-Ideal and sensitivity consideration Analysis of the design of  Fig. 5, upon consideration of non-idealities of CDBA, resulted in oscillator’s characteristic equationto be as shown in (6). Similarly, the effect has been shown on oscil-lating frequency and condition of oscillation through (7) and (8)respectively s 2  s  a 1 d 1 R 3 C  1   1 R 2 C  1    þ  d 1 d 2 b 2 R 1 R 2 C  1 C  2 ¼  0  ð 6 Þ FO  :  - 0  ¼  ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi d 1 d 2 b 2 R 1 R 2 C  1 C  2 s   ð 7 Þ CO  :  R 3  6 d 1 a 1 R 2  ð 8 Þ where  a 1 ,  b 1 , and  d 1  represent the non-ideal port transfer ratios of CDBA1 while  a 2 ,  b 2 , and  d 2  represent the non-idealities of CDBA2. Thesensitivity of thenetwork towards differentpassive compo-nent values, in ideal and non-ideal case, as well as towards thenon-ideal transfer ratios are included in (9)-(11) respectively. Evi-dently, very low sensitivity value, i.e. 0.5, has been obtained whichindicates the efficient performance of the designed configuration. S  x 0 R 1 ¼  S  x 0 R 2 ¼  S  x 0 C  1 ¼  S  x 0 C  2 ¼  12  ð 9 Þ S  - 0 R 1 ¼  S  - 0 R 2 ¼  S  - 0 C  1 ¼  S  - 0 C  2 ¼  12  ð 10 Þ S  - 0 d 1 ¼  S  - 0 d 2 ¼  S  - 0 b 2 ¼  12  ð 11 Þ 5. Parasitic effect Fig. 6 depicts the symbol of a non-ideal CDBA when the para-sitic impedances of all the terminals are involved. Including theseparasitic impedances and considering non-idealities of all ports tobe unity, the circuit shown in Fig. 5 is redrawn and provided inFig. 7. The characteristic equation, of the voltage mode oscillatorcircuit, is given in (12). s 2 þ s  1 C   A 1 R B þ  1 R  Z  1   1 R  A    þ  1 C  B 1 R  Z  2    þ  1 C   A C  B 1 R  Z  1 R  Z  2 þ  1 R B R  Z  2   1 R  A R  Z  2 þ  1 R C  R B   ¼  0  ð 12 Þ The expression for F.O., under parasitic impedances considera-tion, is given in (13) while C.O. was obtained as given in (14). FO  :  x  0  ¼  ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 C   A C  B 1 R  Z  1 R  Z  2 þ  1 R B R  Z  2   1 R  A R  Z  2 þ  1 R C  R B  s   ð 13 Þ CO 1 C   A 1 R B þ  1 R  Z  1   1 R  A    þ  1 C  B 1 R  Z  2   6 0  ð 14 Þ Wherein assumptions have been made that  C   A  ¼ C  1 þ C   Z  1 , C  B  ¼ C  2 þ C   Z  2 ,  R  A  ¼ R 3 þ R P  1 ,  R B  ¼ R 2 þ R O 2  and  R C   ¼ R 1 þ R N  2 .From above derived equations it is evident that presence of par-asitic elements affects the condition and frequency of oscillations.However, error due to these can be avoided if the value of externalpassive components are kept higher than these, when present inseries, and lower than these when present in parallel. In accor-dance with Fig. 7, the value of   C  1   C   Z  1  and similarly the valueof   C  2   C   Z  2 . Also, the value of parasitic resistances at P, N and Wterminals, i.e.,  R P  1 ,  R N  2  and  R W  2  should be very less when comparedto  R 3 ,  R 1  and  R 2  respectively. Hence, all these parasitic resistancesand capacitances will get absorbed and there will be no influenceof the same on frequency and condition of oscillation. 6. Total Harmonic Distortion (THD) analysis Presence of harmonics at frequencies other than the oscillatingfrequency has been evaluated through THD analysis, which is per-formed in Cadence PSPICE software. Summarizing the THD results,when CMOS structure of CDBA is employed, Table 2 has beenprepared. Fig. 5.  Proposed SRCO circuit.  Fig. 6.  Non-ideal CDBA with parasitics at each terminal [16]. T.S. Arora, S. Gupta/Engineering Science and Technology, an International Journal 21 (2018) 43–49  45  The THD results obtained when AD844 were employed for sim-ulations, as per Fig. 2, are tabulated in Table 3. It is evident from the above tables that the value of THD in boththe cases, i.e. CMOS and AD844, is 3.7% and 0.72% respectively.These low valuessupport theefficient functionality of thedesignedSRCO. 7. Simulation results Using the Cadence PSPICE simulation software, all the regularsimulation graphs have been obtained for the purpose of justifyingthe practical workability of the design. Like mentioned before,commercially available I.C. of CFOA, i.e. AD844, as well as CMOSarrangement of CDBA, both have been employed for verifying thepracticality of the devised oscillator network, through simulations.Fig. 4 shows the CMOS structure of CDBA wherein current withan amplitude of 30 m A has been used for  I  B 1 ,  I  B 2  and  I  B 3  and a supplyvoltage ( V  DD  and  V  SS  ) of amplitude ±2.5 V has been applied. Theaspect ratios of all the utilized MOSFETs are provided in Table 4[27], and 0.5  m m MIETEC technology real transistor process param-eters have been used [28].Analysis performed using the CMOS structure of CDBA, as activedevice, resulted in F.O. being 500 kHz with the component valuesbeing adjusted to  R 1  ¼ R 2  = 25 K O ,  R 3  = 22 K O  and  C  1  ¼ C  2  = 12.7pF. The percentage error for this frequency reported to be 4.02.SupportingthetheoreticaldataprovidedforthenovelSRCOcircuit,the transient response as well as the steady state response of it hasbeen included in Figs. 8 and 9 respectively. The two quadratureoutputs generated by the design are shown in Fig. 10. The FFTresponse of the output voltage, which indicates the presence of oscillations at desired frequency, is given in Fig. 11. At last, the Fig. 7.  Proposed SRCO circuit with parasitic elements involved.  Table 2 THD results for CMOS structure of CDBA. Harmonic No. Frequency Fourier Component Normalized Component Phase (  ) Normalized Phase1 5.000E+05 6.931E  01 1.000E+00   9.441E+01 0.000E+002 1.000E+06 2.427E  02 3.502E  02   9.507E+01 9.375E+013 1.500E+06 7.626E  03 1.100E  02   1.515E+02 1.317E+024 2.000E+06 4.469E  03 6.448E  03   1.166E+02 2.610E+025 2.500E+06 2.692E  03 3.885E  03   1.085E+02 3.636E+02DC component = 3.228251E  02Total harmonic distortion = 3.747226E + 00 percent  Table 3 THD results for AD844 implementation of CDBA. Harmonic No. Frequency Fourier Component Normalized Component Phase (  ) Normalized Phase1 1.446E+05 8.371E+00 1.000E+00   1.536E+02 0.000E+002 2.892E+05 1.776E  02 2.122E  03   2.039E+01 2.868E+023 4.338E+05 3.426E  02 4.093E  03   1.759E+02 2.850E+024 5.784E+05 1.914E  02 2.286E  03   3.806E+01 5.764E+025 7.230E+05 4.298E  02 5.134E  03 5.901E+01 8.271E+02DC component =  9.599857E  03Total harmonic distortion = 7.269179E  01 percent  Table 4 Aspect ratios of transistors shown in Figure. 4. Transistors W ( m m)/L ( m m) M  1 – M  10  150/1 M  11 ,  M  12  4/2 M  13 ,  M  14 ,  M  17 ,  M  18  5/1 M  15 ,  M  16  100/1 M  19  20/1 M  20  200/1 Fig. 8.  Transient response using CMOS structure of CDBA as active device. Fig. 9.  Steady state response attained using CMOS structure of CDBA.46  T.S. Arora, S. Gupta/Engineering Science and Technology, an International Journal 21 (2018) 43–49
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