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A+Steady State+Thermal+Impedance+Model+for+Thermal+Coupling+of+High Power+Press Pack+IGBT+Module

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A+Steady State+Thermal+Impedance+Model+for+Thermal+Coupling+of+High Power+Press Pack+IGBT+Module
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  A Steady-State Thermal Impedance Model for Thermal Coupling of High-Power Press-Pack IGT Module !in "#I $ % &ei 'I $ %(ongsheng !) * % ing &)+ * % "ei ,HAG $ % #rping .#G $   /$0orth China #lectric Power )ni1ersity% Changping .istrict% ei2ing $3**34% China *0 #lectric Power 5esearch Institute of China Southern Power Grid% Guang6hou 7$3383%China9  Abstract   —Reliability of Power electronic modules is a critical criterion for HVDC converter valve. Developing a thermal resistance equivalent networ which can be integrated with electrical model to predicted !unction temperature is considered a effective way. "s for press#pac $%&' module( the compact layout of the module maes the thermal coupling between the chip would not be ignored. $n addition( the double side heat dissipation maes the heat sin parameters have a certain influence on the thermal equivalent model of $%&' module. 'hus , ,, ,  the traditional method of the thermal equivalent circuit model( by which all chips are regarded as one regardless of the thermal influence of the chip( and modeling of heat sin and $%&' respectively is not applicable for press#pac $%&' module. $n this paper( the necessity of the overall modeling of $%&' and heat sin is proposed( then a new thermal model of $%&'#heat sin with )ulti chip thermal coupling parameters is presented based on *#D finite element simulation( and the model parameters can be ad!usted with the flow rate of cooler. 'he simulation results show that the proposed model has high accuracy in different operating conditions and heat dissipation conditions. )oreover( the thermal equivalent matri+ elements can also be used in the analysis of thermal coupling characteristics( such as flow effect of water cooled heat sin and chip power loss ratio.  Index Terms  —Press#pac $%&' module( ,inite element simulation( thermal coupling equivalent circuit model( !unction temperature prediction I0   I  T5+.)CTI+  The 1oltage source con1erter with the insulated gate :ipolar transistor /IGT9 modules has :een widely used in H;.C transmission system0 Compared with the traditional welding IGT% press-pack IGT/PPI9 module with many e<cellent characteristics% such as the dou:le-sided cooling% short circuit failure and high relia:ility% has a good prospect in Higher  power H;.C con1erter 1al1e =$> 0 The relia:ility of the IGT module is important to the safe operation of H;.C transmission system0 The 2unction temperature has strongly influence on :oth de1ices characteristics and its lifetime and :alanced distri:ution of heat  produces strong thermal constraints to impro1e the capacity and efficiency of the IGT0 Howe1er% it is difficult to directly measure the 2unction temperature :y e<periments =*> 0uilding a thermal 5C e?ui1alent network which can :e integrated with electrical model to predicted 2unction temperature is considered a effecti1e way =@-7%%$3> 0 At present% the research on the 2unction temperature  prediction is more focused on traditional IGT0 In=@-B>% with the transient thermal impedance cur1es pro1ided :y the manufacturers% a oster-type network can :e o:tained 1ia cur1e-fitting for electro-thermal methodology model0 "hile =7>o:tains the cur1e :y @-. finite element simulation :ased on the physical structure of .e1ices% not only for IGT :ut heat sinkDs  thermal   e?ui1alent model  can :e got 1ia cur1e-fitting0 =4> urther pointed out that it is necessary to model IGT and heat sink as whole in AS(S% and then to e<tract parameters% otherwise it will result in increased error0 Howe1er% the a:o1e models do not take into account that the diode and the IGT chips are thermally coupled% which makes the predicted  2unction temperature much lower0 ased on the finite element simulation of welding IGT% a thermal e?ui1alent coupling network model and the method of e<tracting the parameters are  presented  =E> 0 The method is applied to the IGT module of electric 1ehicle% and the influence factors of thermal coupling are studied :y =8>0 A new circuit topology which can accurately reflect the characteristics of mutual thermal resistance is  proposed in the paper =>0 ut the a:o1e is only for single IGT modules% less considered the impact of heat sink dynamic  performance on the 2unction temperature and thermal coupling in module% which need o1erall modeling of IGT and heat sink   =$3> 0 The pro:lems mentioned a:o1e are more serious for  press-pack IGT with multi chip compact layout and dou:le-sided cooling0 Therefore% this paper mainly proposes a new thermal model of IGT-heat sink considering multi chip thermally coupled% which parameters can :e ad2usted with the flow rate of cooler% :ased on @-. finite element simulation of a IGT module-heat sink o1erall model0 The main contri:ution of this model is to consider thermal coupling factors% flow adapti1e parameters and integrated modeling of heat sink and IGT0 The simulation results show that the proposed model has high accuracy in different operating conditions and heat dissipation conditions0 Moreo1er% the thermal e?ui1alent matri< elements can also :e used in the analysis of thermal coupling Pro2ect Supported :y the ational atural Science undation of China /7$*EE3479   2016 International High Voltage Direct Current Conference (HVDC 2016)Shanghai,25-27 Oct. 2016HVDC 2016Paper No.CP0247 Page 1/6  552   characteristics0   II0   TH# ST5)CT)5# A. TH#5MA& I#&. AA&(SIS + PPI  M+.)&#  A.   The Physical Structure of PPI Module and its Liquid Cooling The multi chip parallel connection structure is usually adopted in the IGT module0 igure $ shows the internal structure of a PPI module with water cooler used in 1oltage source con1erter and the chip layout0 In *733;-@43A  press-pack IGT-diode pairs /T3@43*7A9% there are 7 IGT and * diode independent capsules% each chip through se1eral layers of materials connect to collector-side and emitter-side% the material parameters are gi1en in Ta:le $%the heat of each chip might affect the other through :ase plate0 The cooler adopts upper and lower spiral flow passage structure0 /a9 simplified representations of a press-pack module with cooler 󰁆󰁒󰁄 󰁔  󰀱 󰁆󰁒󰁄 󰁔  󰀲  󰁉󰁇󰁂󰁔 󰁔  󰀳  󰁉󰁇󰁂󰁔 󰁔  󰀵  󰁉󰁇󰁂󰁔 󰁔  󰀶  󰁉󰁇󰁂󰁔 󰁔  󰀴  󰁉󰁇󰁂󰁔 󰁔  󰀷  󰀹󰀮󰀴󰁭󰁭 󰀱󰀴󰁭󰁭    (   : )  chip layout and flow channel structure ig0$0 The internal structure 1iew of the IGT module Ta:le IF Physical Parameters of IGT module T3@43*7A &ayer material Thermal-conducti1ity =" 0 m -$0   -$ > C   p  = 0 kg -$0   -$ > ρ  =kg 0 m @ > Thickness =mm> IGT chip Si $B8 E3@ *@*80@ 30@$ 55 chip Si $B8 E3@ *@*80@ 30@$ I Mo $@8 *77 73 $0$ III Mo $@8 *77 73 $0EE7 I; Ag B*E *@B $3733 30$7 ; Cu *3*0B 8E$ *E$ 80B$ ase plate Cu *3*0B 8E$ *E$ E03* ;I 󲀔   - - - 30$7  B.   Thermal Analysis of IGBT Module Based on F Method and !erification $0   The thermal # model "ith the parameters gi1en in section A% thermal data ha1e  :een generated :y numerical models :uilt up e<ploiting the AS(S% a commercial #-:ased software0 In order to confirm the 1alidity of # model% the transient thermal impedance cur1es e<tracted from the model without heat sink is compared with ones pro1ided :y manufacturers data sheet0 To do the following Simplified in simulationF $9 power modules are typically made :y thin 1ertical layers and the thermal conducti1ity of ceramic shell is small% It means that the heat flu< predominantly flows from the chips to :ase plate of the module0 Therefore% the flu< through the lateral sides can :e neglectedJ *9 layers are directly connected through the pressure0 In addition to the thermal resistance of each layer% there is thermal contact resistance :etween the 1arious components% which can :e e?ui1alent to the thin layers on the :oth sides of the chip0 The material parameters of the thin layers would :e o:tained according to the e<perimental cur1e analysis0 According to the simulation results of a MMC-H;.C electrical system  =$$> % the power loss distri:uted is $*08" on each IGT and *3" on diode% the en1ironmental temperature is E3 degrees0 Since the transient thermal impedance  "c  #   − is defined as /$9% the o:tained #M temperature distri:ution result can :e post processed to deri1e the transient thermal impedance cur1e% for :oth IGT and diode can :e calculated0 /9/9/9  "c "c tt t  P  TT  #   − −=  /$9 T  is ma<imum 2unction temperature of se1eral IGT /or a diode9 chips at e1ery moment % c T  is the ma<imum of the case temperature% P is the total loss of se1eral IGT /or diode9 chips0 igure * shows the comparison results of the transient thermal impedance cur1es deri1ed :y # model and datasheet0 It can :e seen that the addition of the thermal e?ui1alent resistance layer makes the two kinds of cur1es fit well0 Therefore% it is considered that the # thermal model and the simulation method can :e used to reflect the thermal characteristics of the IGT0 #mitter/measure9Collector/measure9.ou:le/measure9   ig0 * Comparison of transient thermal impedance cur1es deri1ed :y # model and datasheet +n the :asis of the a:o1e IGT model% a water cooled heat sink is added% and the o1erall simulation model of the module and heat sink is esta:lished0 Set the inlet into 1elocity and 2016 International High Voltage Direct Current Conference (HVDC 2016)Shanghai,25-27 Oct. 2016HVDC 2016Paper No.CP0247 Page 2/6  553    temperature control% water flow is *&Kmin% temperature of inlet water is E3 ℃  % outlet for constant pressure control0 And make the water and solid part of sink solid - li?uid coupled on the conser1ation of energy constraints0 Comparison of the 2unction temperature results of the o1erall model and modeling of heat sink and IGT respecti1ely /for split modeling% the heat transfer in the contact surface of  :ase-plate and heat sink is uniform% the connection condition of the two models is the a1erage temperature of the contact surface09 It can :e seen in Ta:le II that e1en power loss difference :etween IGT and diode is small% 2unction temperature error for split modeling reaches a:out $3L0 This is  :ecause for PPI IGT with dou:le-sided cooling% the heat sink Characteristics% such as flow design and water flow rat% not only affect their own heat capacity% also ha1e a greater impact on the heat flow distri:ution inside the module% there:y affecting its thermal resistance0 In addition% the contact resistance and spreading thermal resistance of the module to the heat sink are neglected0 Therefore% it is necessary to esta:lish the o1erall simulation model of the IGT module and the radiator0 Ta:le IIF Comparison of the 2unction temperature results of the o1erall model and split modeling temperature rise/ ℃  9 △  T$ △  T* △  T@ △  TB △  T7 △  T4 △  TE +1erall model 803B 80$E 404@ 407 404$ 4047 4077 Split modeling E0B* E0@4 70B 70B 70E 70* 708 #rror /L9 E04@ E04@ $30BE 0E@ 04$ $$037 8044  oteF the error in this paper is :ased on the ma<imum 2unction temperature rise of the similar chips0 *0   Analysis of the influence of thermal coupling The o1erall model is used to simulate the temperature of the chips in two conditions% chip$ to E works separately and se1en chips work simultaneously0 In order to compare the results% set the power loss of each chip *3"0 Ta:le III the temperature rise of E chips when chip @ works alone Chip △  T$ △  T* △  T@ △  TB △  T7 △  T4 △  TE temperature rise/ ℃  9 30* B08$ 308E 3087 304B 308* 304@ Ta:le I;F Comparison of the temperature rise :etween single chip working and multi chip working Temperature rise/ ℃  9 △  T$ △  T* △  T@ △  TB △  T7 △  T4 △  TE Single chip work 70@ 70BB B08$ 70B* 70E 70*E 70E7 Multi chip work 033 0B4 07@ 0B$ 0E3 047 04@ #rror/L9 B3L B@L 73L B*L B3L B7L B3L The following conclusions can :e drawn from the a:o1e ta:leF $9 The thermal power generated :y one chip causes the heating of :oth that chip and all the others in the package0 *9 The temperature difference :etween when single chip works and when chips work simultaneously is caused :y other chip on the thermal coupling0 .ue to the compact layout% the error is up to B3L when the chip loss is same% and that effect could not :e neglected0 In 1iew of the e<isting thermal network model :ased on datasheet data can not consider heat coupling of the non similar chips% the model is not suita:le for PPI0 Therefore% it is necessary to study a new thermal model of IGT-heat sink considering multi chip thermally coupled0 III0   . #5I;IG T H#5MA& C +)P&IG # ')I;A&#T   #T"+5   +wing to the heat in the module flu< predominantly flows from the chip to the heat sink% the heat transfer pro:lem can :e assumed to :e linear0 In this condition% the superposition  principle can :e used0 rom the analysis a:o1e% it is known that the temperature rise of a chip is caused :y its own power and the coupling power of the others0 Therefore% the circuit theory is a1aila:le to descri:e the pro:lem as /*9 %and then the thermal e?ui1alent circuit model is o:tained 0 $$$$*$$**$****$* nnnnnnnn ref  T$$$P T$$$P T$$$P  T                 = +                     ……⋮ ⋮ ⋮ ⋱ ⋮ ⋮⋯ i   (  * )   "here% T   is the chip 2unction temperature%  P   is the power applied on chip i % ref  T   is the reference temperature and [ ] th  $  is the n  n thermal resistance matri<% called thermally coupled e?ui1alent matri< /#TCM90 According to the heat source of the chip temperature rise% the response i  $   is named thermal self resistance% which is temperature rise of chip i response to its own heated0 "hile%  "  $  is named thermal mutual impedance/or coupled thermal resistance9 and represents the thermal coupling effect :etween the two considered de1ices0 They can :e calculated :y /@90 ref i ii TT  P   $ − =   ;   "ref  " i" TT  P   $ − =   (  @ )   $0   Parameter e<traction of thermally coupled e?ui1alent matri< The thermal :eha1ior of the module may :e therefore o:tained :y assuming% at each time% only one de1ice acting as a heat source and e1aluating the temperature along the module0 The procedure is then repeated for each de1ice of the module and the results are added to o:tain the complete thermal response0 .ifferent from the traditional method% the temperature of water inlet is selected as the reference temperature to e<tract the  parameter of the o1erall thermally coupled e?ui1alent model of IGT and heat sink0 It is :ecause for press-pack IGT% $9 flow design of cooler may make different locations of the heat capacity differencesJ /*9 there may :e much differences  :etween IGT and diode power loss under different conditions %such as the MMC-H;.C system% which makes the temperature distri:ution of the case much different0 And using the a1erage of case as the temperature node to deri1e the IGT and the heat sink e?ui1alent circuit respecti1ely is 1ery limited0 So% this paper chooses the temperature of water inlet to e<tract  parameters of [ ] th  $ with /@90 *0   Impro1ed parameter e<traction method of e?ui1alent thermal coupling matri< In the practical H;.C system% the water flow of heat sink is 2016 International High Voltage Direct Current Conference (HVDC 2016)Shanghai,25-27 Oct. 2016HVDC 2016Paper No.CP0247 Page 3/6  554   changed as the controlla:le 1aria:le to ensure the relia:le operation of power de1ices under different operating conditions0 Simulation results show that not only for the cooler also the  power module /solid9% its thermal resistance will change with water flow rate0 Therefore% in order to ensure the uni1ersal applica:ility of the e?ui1alent model% it is necessary to make further impro1ement on the thermally coupled e?ui1alent matri< parameter e<traction method introduced in sectionC0$0 Thermally coupled e?ui1alent matri< =  $ > #TC  could :e transformed into matri<=  $ 3 > and matri<=  $ % >0 =  $ 3 >called inherent resistance matri< that does not change with the flow of the heat sink and =  $ % > is an additional thermal resistance matri< determined :y the heat sink flow0 [ ] 3 % TC   $ $$  = +       (  B )   ased on the :asic formula of heat transfer% the relationship  :etween the general con1ecti1e heat transfer resistance con&  $  and the flow rate % can satisfy /790 30EBE30BE*30BE $JJ303@eJJ@5eB con&con& '  $h(uhS) (u*r$%u)) $%u  ρ  −  = =   = ⇒ ∝ πµ = =     (  7 )   Therefore% :ased on method in section0C$% the thermally coupled e?ui1alent matri< =  $ > #TC  under different flow rate can  :e o:tained0 And to analy6e the 1ariation law of each element of the matri< with 30EBE % − % we can see that the thermal self resistance and thermal mutual impedance are linearly related to 30EBE % −  from igure B0 Then the formula /B9 can :e deri1ed to formula /49 :y linear fitting any two =  $ > #TC  under different flow0 [ ] 3 30EBE3 % TC   $% $$  −  = + ⋅       (  4 )   =  $ 3 >and =  $ '3 > are :oth constant matri<% which are only related to the solid material and geometry of IGT and heat sink0 % -30EBE /&Kmin9 -$      $     i    2     /    G    K   w    9  ig0 B the e?ui1alent thermal resistance matri< elements change with the 30EBE % −   I;0   ; A&I.ATI+ + TH# TH#5MA&&( C+)P&#. #')I;A&#T M+.#& A. AA&(SIS + I&)#C# ACT+5S + TH#5MA& C+)P&IG    A.   !alidation of thermal cou*led equi&alent model $0   The applica:ility of the model under different operation conditions rom the simulation result of a MMC-H;.C electrical system ,  we can take three typical power loss data of PPI under different operation conditions0 Set the power loss as chipDs heat source% water flow is *& Kmin% inlet water temperature is E3 ℃󰀮󰀠 "ith the impro1ed thermal coupled e?ui1alent model /I-#TC9% traditional e?ui1alent model deri1ing from datasheet cur1e and # model% the 2unction temperature of chips could :e calculated respecti1ely0 The results are compared in Ta:le ;0 Ta:le ; F unction temperature of chips under different conditions (℃)    Power  (  " )   Method .iode IGT #rror  ma< /L9 (  .KIGT )  T  $   T  *   T  @   T  B   T  7   T  4   T  E  P T N* P . N47 #M 30E4 880 E7087 E70E EB0@B EB0B EB0*E K I- #TC 30E8 803$ E7088 E707 EB0B3 E703$ EB0@@ 3088K*0E .atasheet 8*084 E3083 @8K84 P T NBB P . NB #M EE0$E E0B 8E04 8E043 80$ 880E3 8034 K I- #TC EE0*E E04B 8E0EE 8E0E3 80@8 880E 80$4 $0K30 .atasheet E30E 8E04@ $K$E P T N$*08 P . N*3 #M E803B E80$E E404@ E407 E404$ E4047 E4077 K I- #TC E8034 E80*3 E404B E404B E404@ E404E E4078 30@EK30E7 .atasheet E@04 E70$@ 7$K**  oteF the error in this paper is :ased on the ma<imum 2unction temperature rise of the similar chips0 #1en power loss are much different :etween IGT chip and diode chip /module heat distri:ution is e<tremely une1en9% the chip 2unction temperature calculated :y impro1ed thermal coupling e?ui1alent model is accurately0 "hile :y traditional e?ui1alent model deri1ing from datasheet cur1e% the result error is :ig0 *0   The applica:ility of the model under different water flow rate The chip 2unction temperature is calculated under different flowrate with thermal coupling e?ui1alent model% impro1ed thermal coupling model and # model0 The results are recorded in Ta:le ;I0 It can :e seen that the thermal coupling e?ui1alent model can only accurately calculate the 2unction temperature under certain water flow rate% and the impro1ed thermal coupling e?ui1alent model can :e applied to any flow rates0 Ta:le ;I F unction temperature of chips under different ' (℃)    low rate Method T  .$   T  T@   #rror  ma< (  L )   *&Kmin #M E033 E0B4 O #TC E03B E073 308$ I-#TC E80 E0BB 30@* B&Kmin #M EE08B E80*8 O #TC E03B E073 $B044 I-#TC EE0@ E80@ $0** 2016 International High Voltage Direct Current Conference (HVDC 2016)Shanghai,25-27 Oct. 2016HVDC 2016Paper No.CP0247 Page 4/6  555     B.   Thermal cou*ling influence factor analysis The thermal coupling e?ui1alent model can not only  predict the 2unction temperature of the chip% :ut also can :e used to analy6e the thermal coupling ?ualitati1ely0 A parameter that can reflect the degree of thermal coupling :etween the chip is defined% named thermal coupling coefficient Th couple/L9  "+i F /L9  $33L ii  ""cou*leii  "i  #P  #P  Th  ⋅⋅ − = ×   (  7 )   This parameter means for the chip i % the temperature rise caused :y another chip  "  thermal power is reference to the temperature rise caused :y the chip itself0 where%  #  i" 、   #  ii are mutual thermal resistance and thermal resistance in e?ui1alent thermal coupling matri<%  P  i 、   P   "  are the heating power of chip i,"  0 In addition to the corresponding influencing factors for a single 1aria:le% the other simulation conditions of # model are set as sectionII% the power ratio of the chip is $0 $0   Influence of chip power loss ratio Assuming only chip $ and * works% the total power is $33"0 igure 7 shows for chip$ the Th couple/L9 *$ and the temperature rise caused :y chip* are changed with the power loss ratio of the two chip0 It re1eals that the greater the relati1e  power of the chip% its thermal coupling to other chips is more significant% whereas the thermal coupling effect is more limited0 "hen the power difference of the two chips is larger% the thermal coupling of the higher-power chip is mainly considered% and the thermal coupling of the lower-power chip can :e ignored0    P  -   P  /  △      T    c   o   u   p    l   e     K  △      T     $  (     L  )  T  h    c  o u  pl    e   /    L  9    *  -$     ig0 7 the thermal coupling and the coupling temperature rise with the change of the  power ratio of the chip *0   low effect of water cooled heat sink Change the heat sink inlet flow from 30E&Kmin to B&Kmin0 "ith igure 4% it can :e seenF $9 "ith flow increasing the o1erall thermal resistance decreases and the coupling degree  :etween chip decreases% which is conduci1e to the modules heat loss% :ut at the same time will increase the operation cost of the cooling systemJ *9 "hen the inlet flow is less than $0B&Kmin% increasing the flow unit can effecti1ely impro1e the heat dissipation module capacity% and when the flow is greater than $0B&Kmin% the function is much more limited% so it is wise to select the flowrate considering :oth economical efficiency and thermal coupling coefficient0      T      h    c   o   u   p    l   e    /    L    9 % /&Kmin9 $  i     2      /   G K    w  9    Th couple/L9 *-$  $ $$  $ $*   ig0 4 the thermal coupling degree of the chip and the heat resistance of the chip changes with the heat sink flow ;0   C+C&)SI+  In this paper% a new thermal model of IGT-heat sink with Multi chip thermal coupling parameters is presented :ased on @-. finite element simulation% and the model parameters can :e ad2usted with the flow rate of cooler0 The thermal e?ui1alent matri< elements can also :e used in the analysis of thermal coupling characteristics0 The following conclusions can :e o:tainedF $9 Impro1ed thermal coupling e?ui1alent matri< has uni1ersal applica:ility to predict the chip 2unction temperature  prediction under different operation conditions and heat sink flow rate0 *9 Thermal coupling coefficient is introduced to e1aluate the degree of thermal coupling :etween chips% which can :e o:tained with thermal self resistance and thermal mutual resistance0 "ith this parameter% se1eral factors that affect thermal coupling can :e ?uantified :y analysis% and according to the law of the analysis% we can put forward useful suggestions to thermal e?uili:rium of heat dissipation and module0 @9 The thermal coupling :etween the two chips is not only affected :y the physical structure and parameters% :ut also to a large e<tent related to the power ratio of the chip /i0e0% the running state90 The thermal coupling effect of high power de1ices to others is more significant0 or the two de1ices with large power difference% the thermal effects of small power de1ices can :e ignored0 5  ##5#C#S   =$>   .ou ,echun% !in (uen% &iu Guoyou% et al0 QThe Thermal Characteristics of Press-pack IGT moduleR =>0 #lectric .ri1e for &ocomoti1es % 1ol03@%  pp04-%May%*3$@0 =*>   (ang S% !iang .% ryant A% et al0 QCondition Monitoring for .e1ice 5elia:ility in Power #lectronic Con1ertersF A 5e1iewR=>0 I### Trans on Power #lectronics% 1ol0*7/$$9% pp0*E@B-*E7*%*3$30 =@>   !u Mingwei% ,hou % .u !iong% et al0 QSimulation and e1aluation of insulation gate :ipolar transistor in insulated gate :ipolar transistor in three-phase in1erterR =>0 ournal of Chong?ing )ni1ersity% 1ol0@E% no0 3*%pp0 @E-B7% e:ruary %*3$B0 =B>   Tu 'ingrui% !u ,heng0 QModular multile1el con1erter :ased H;.C transmission 1al1e loss assessment using the method of 2unction temperature feed:ack Q=>0High ;oltage #ngineering% 1ol0@8% no04%une%*3$*0 =7>   "ang H% ham:adkone A M% (u !0 Q.ynamic electro-thermal modeling in Power #lectronics uilding lock /P#9 applicationsR=C>0 #nergy Con1ersion Congress and #<position0 I###% *3$3F*@-@3330 2016 International High Voltage Direct Current Conference (HVDC 2016)Shanghai,25-27 Oct. 2016HVDC 2016Paper No.CP0247 Page 5/6  556
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