A W-band CMOS Receiver Chipset for Millimeter-Wave Radiometer Systems

A W-band CMOS Receiver Chipset for Millimeter-Wave Radiometer Systems
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  378 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011 A W-band CMOS Receiver Chipset forMillimeter-Wave Radiometer Systems Lei Zhou  ,StudentMember,IEEE  , Chun-Cheng Wang  ,StudentMember,IEEE  , Zhiming Chen  ,StudentMember,IEEE  ,and Payam Heydari  , Senior Member, IEEE   Abstract— This paper presents a W-band receiver chipset forpassive millimeter-wave imaging in a 65 nm standard CMOStechnology. The system comprises a direct-conversion receiverfront-end with injection-locked tripler and a companion analogback-end for Dicke radiometer. The receiver design addresses thehigh 1/f noise issue in the advanced CMOS technology. An LOgeneration scheme using a frequency tripler is proposed to lowerthe PLL frequency, making it suitable for use in multi-pixel sys-tems. In addition, the noise performance of the receiver is furtherimproved by optimum biasing of transistors of the detector inmoderate inversion region to achieve the highest responsivity andlowest NEP. The front-end chipset exhibits a measured peak gainof 35 dB, 3 dB BW of 12 GHz, NF of 8.9 dB, while consuming94 mW. The baseband chipset has a measured peak responsivity( ) of 6 KV/W and a noise equivalent power (NEP) of 8.54pW Hz 12  . The two chipsets integrated on-board achieve a totalresponsivity of 16 MV/W and a calculated Dicke NETD of 1K witha 30 ms integration time.  Index Terms— CMOS, detector, frequency conversion, mil-limeter-wave, 94 GHz, passive imaging, radiometer. I. I NTRODUCTION M ILLIMETER-WAVE (MMW) radiometers have beenaround since the 1960s. Nevertheless, only recentlyreal-time MMW imaging techniques have become increasinglymore attractive to the military and the public as a result of rapid progress in monolithic MMW integrated circuit tech-nologies [1]. Applications of MMW imaging include remotesensing [2], security surveillance [3], and nondestructive in-spection for medical and environment field [4], [5]. PassiveMMW (PMMW) imaging is specifically attractive because itsdetection of emitted thermal radiation from a scene reducespublic health concerns for medical applications and securityconcerns for military applications [6]. Current imaging sys-tems using mechanical scanning employ high-performancelow-noise receivers (RXs) implemented in III-V compoundsemiconductor technologies with low-level of integration.Benefiting from silicon technology scaling, the continuingincrease in enables the integration of highly complex MMW Manuscript received March 05, 2010; revised November 06, 2010; acceptedNovember 06, 2010. Date of publication January 06, 2011; date of currentversion January 28, 2011. This paper was approved by Associate EditorJacques Christophe Rudell. This work was supported in part by an SRCcontract 2009-VJ-1962 and by an NSF grant ECCS 1002294.The authors are with the University of California at Irvine, Irvine, CA 92697-2625 USA (e-mail: versions of one or more of the figures in this paper are available onlineat Object Identifier 10.1109/JSSC.2010.2092995 systems, such as 60 GHz high data rate wireless communica-tion [7], [8] and 77 GHz automotive radar system [9]–[11],in a single die. Moreover, high packing density of silicon(and in particular, CMOS) technologies enables the possibilityof building low-cost multi-pixel focal plane array (FPA) forPMMW imaging at W- and D-band frequencies. Several MMWfront-ends have been developed for imaging systems [12]–[16],while a 94 GHz SiGe PMMW imaging IC with integrateddetector is reported in [17].CMOS,withitssuperiorintegrationcapabilityandlowercostin high volumes, is poised to be the ultimate solution for a fullyintegratedPMMWimagingsystem.Nevertheless,high1/fnoiseofMOSpowerdetectors (usedinan allCMOSimplementation)necessitates the use of a switched-based Dicke system. In [18],a 94 GHz CMOS PMMW imaging is demonstrated. However,due to the inherent lower available gain and higher 1/f noise, thecircuit performance in [18] may not meet a practical PMMWimaging’s sensitivity requirement. To address these challenges,ahigh-gain,low-powerW-banddirect-conversionfront-endRXis presented. The proposed chipset incorporates an injection-locked tripler for LO generation and an analog back-end de-tector realizing a Dicke radiometer in a 65 nm standard CMOSprocess. This prototype mitigates the aforementioned issues atboth architecture- and circuit-level design, demonstrating thefeasibility of using CMOS for future generations of low-costmulti-pixel portable passive imaging cameras.Theremainderofthispaperisorganizedasfollows.SectionIIdiscusses the background and design requirement for PMMWimaging system. In Section III, we describe the RX architectureand system-level considerations for CMOS implementation.The design and analysis of the RX front-end and detector base-band chipsets are described in Sections IV and V, respectively.Measurement results of the RX are presented in Section VI.Finally, Section VII provides concluding remarks.II. S YSTEM C ONSIDERATION  A. Radiometer Background  The radiometer employs a very sensitive RX to detect thepower ( ) emitted from the radiating object which can be ex-pressedas , where is thenoise-like inputsignal(called signal-noise throughout the paper) power the RX col-lects, is the bandwidth of the front-end RX and is theeffective radiometric temperature [6]. For imaging application,the input temperature range of the radiometer is 0–313K [19].The main parameter in the radiometer design is the sensitivityof the constituent RX. Noise equivalent temperature difference(NETD), which is a measure of the sensitivity, is defined as the 0018-9200/$26.00 © 2011 IEEE  ZHOU et al. : A W-BAND CMOS RECEIVER CHIPSET FOR MILLIMETER-WAVE RADIOMETER SYSTEMS 379 effective radiometric temperature difference , producing aDCvoltageattheRX’soutput,whichisequaltothermsvalueof theoutputfluctuationsdue totheRXnoise[20].GiventheRX’snoise temperature , the relationship between NETD andis expressed as [20](1)where isthebandwidthoftheRXfront-endand istheintegration time at the baseband. In order to generate real-timeimages, the integration time of the imager should not be greaterthan about 10–25 ms [21]. For instance, if GHzand ms, the RX with a of 3000K will havean NETD of 0.21K. For a radiometer used in imaging appli-cation, the NETD must be less than 1K for acceptable imagequality [22].  B. Dicke Radiometer  The RX’s NETD is lowered by increasing either or. Ideally, the output fluctuation can be reduced by in-creasing the integration time. However, when integration timereaches milliseconds to seconds range, gain variation in thehigh-gain amplifier can no longer be neglected. This is becausethe RX cannot differentiate the output voltage change causedby gain variation from the change in the input signal-noisepower. Therefore, the NETD of the RX is expressed as [20](2)where is the effective gain variation and is the averagepower gain. For example, the RX with a 3000K system noisetemperature indicates an NETD of 3K if the average 30 dB( ) front-end gain increases by 0.004 dB. To improve accu-racy of the radiometer, the Dicke RX is chosen to solve thegain fluctuation [23]. A Dicke switch is inserted at the front-endinput rightaftertheantennatoswitch betweentheinputantennaand a reference load. As the modulation frequency is higherthan the gain fluctuation frequency, it is possible to detect thesignal-noise in the presence of gain variation. Since the RXonly receives the input signal-noise one half of the time, the RXsensitivity is degraded as a trade-off of using Dicke RX archi-tecture, i.e., . Although the DickeRX’sNETDistwicethatofanidealradiometer(obtainedaboveto be 0.21K), the 0.42K Dicke NETD is still much lower thanthe 3K NETD caused by the 0.004 dB gain variation. Note that,in an imaging system, the noise temperature from thermal back-ground,antennaloss,SPDTDicke switchloss,and interconnectlossshouldalsobeaccountedforintheNETDbudget.Sincethesignificance of some of these sources of loss depends on the im-plementation and is usually the main contributor to the totalnoise temperature of the system, only is used in NETD cal-culation. The Dicke switch loss also degradesthesystem NETDand its effect will be explained in more detail in Section III-D.III. PMMW I MAGING R ECEIVER A RCHITECTURE  A. Direct-Conversion Receiver  Traditionally, PMMW imaging RX employs two types of ar-chitectures: direct detection [17], [24] and frequency conver-sion(e.g.,directconversion,heterodyne,andetc)[25].TheSiGeBiCMOS technology is the best platform to implement a prac-tical PMMW system using direct-detection structure, as shownby a number of recently published works (including a paper re-cently presented in [26]). However, in the current 65 nm CMOSprocess, the insufficient front-end gain, poor isolation, and poordetector noise performance at 94 GHz prevent the use of direct-conversion architecture to design a practically viable PMMWsystem.Instead,adirect-conversionarchitecturemeetsthestrin-gentnoiseandgainrequirementsofaPMMWsystem.AlthoughSiGe BiCMOS provides better performance, the CMOS MMWfront-end can be seamlessly integrated alongside digital base-band circuit, thereby leading to a low-power and high perfor-mance system.Since there is no phase information in the received signal-noise,thedirectconversion(withanLOfrequencyexactlyinthemiddleofthewideRFband)does notnecessarilyneed I/Qpath.Moreover, the baseband bandwidth is reduced to one half of theRF bandwidth because of the frequency folding. Therefore, theproposed RF front-end chipset uses direct-conversion architec-ture to reduce chip area, as the wide bandwidth (e.g., 10 GHz)and high gain (e.g., 20 dB) requirements for an IF amplifier in aheterodynearchitecturerequiremaximizingthegain-bandwidthproducts, thereby mandating the use of bulky inductors (as partof series and/or shunt peaking passive networks) for bandwidthenhancement. Phase-locked loop (PLL)-based frequency syn-thesizers are commonly used [27] to generate the LO signal in afrequency conversion RX for wireless communication applica-tions. An injection-locked frequency tripler has been chosen togenerate the LO signal from the low frequency external source.The proposed LO generation scheme reduces the LO frequencyto 30 GHz, making it markedly easier for routing/distributionand enabling LO sharing in a multi-pixel imager.The high gain requirement in the PMMW RX is due, in part,to a large noise floor of the detector. It is, therefore, necessarytominimizethedetector’snoiseequivalentpower(NEP)(whichis a measure of the detector’s sensitivity) so as to reduce the re-quired pre-detector’s amplifier gain. Responsivity measures thedetector’s gain, defined as the output DC voltage divided by theincident power to the detector, while the NEP is calculated asthe RMS output noise voltage divided by the detector’s respon-sivity (see Sections V-A and V-B). In this design, a basebanddetector, comprised of transistors biased in moderate inversion,is proposedto achievebetterresponsivity and lowerNEP.Inad-dition, a baseband detector achieves lower NEP compared to anRF detector, which is another reason why direct-conversion ar-chitecture is chosen.Fig. 1(a) shows the block diagram of the direct conversionPMMW imaging RX. A two-chip solution is chosen to ensuretestability at both system- and circuit-level. The chopped inputsignal with frequency band from 80 to 92 GHz is amplified bya five-stage common-source (CS) LNA. The amplified signal ismixed down to 0.1–6 GHz frequency band by an 86 GHz LO  380 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011 Fig.1. PMMWimagingchipset.(a)Blockdiagram.(b)Waveformsatdifferentnodes. signal provided by the frequency tripler. After frequency con-version, the chopped signal is amplified by a two-stage wide-band amplifier. The signal is then fed to the baseband chip,which performs energy detection, synchronization and integra-tiontogeneratetheoutputvoltageproportionaltothescenetem-perature. The wideband detector converts the chopped and am-plifiedsignalfromthefront-endchipintoa100MHzmodulatedbaseband signal, which is then amplified by a variable-gain am-plifier (VGA). A baseband chopper, which is synchronized tothe front-end chopper, converts the modulated signal into a con-stant DC level using a 500 kHz low-pass filter.  B. 1/f Noise OneimportantissueregardingadvancedCMOSprocessisthehigher 1/f noise corner frequency compared to III-V and SiGecompound semiconductor technology. 1/f noise causes DC driftat the RX’s output, which affects the RX’s NETD in a similarway as the RX’s gain fluctuation, and thus will be alleviatedusingDickearchitecture.Byincreasingtheswitchingfrequencyhigher than the 1/f noise corner frequency, the 1/f noise con-tribution on the RX’s NETD will become negligible. The 1/f noisecornerina65nmCMOSprocessisbetween100MHzand1 GHz. Conventional mechanical chopper with electronic-waveabsorber has a maximum speed limit of around 200 Hz [28].Because of its faster switching speed, an electronic switch isthus preferred to reduce the RX’s NETD. Fig. 2 shows mea-sured output noise spectrum of the detector along with 1/f noisefitting line. The detector noise floor, measured using the spec-trum analyzer, is captured from 100 kHz to 100 MHz with res-olution bandwidth (RBW) of 1 Hz. As shown in this figure,at 30 MHz, the noise PSD is approximately 5 dB higher than Fig. 2. Measured output noise of the detector with curve fitting. that at 100 MHz corner frequency. This means that switching at30 MHz still greatly reduces the 1/f noise. C. Phase Noise Since the received signal is downconverted to a zero-IF fre-quency by an LO signal, inevitably the oscillator noise is alsodownconverted, which affects the noise floor of downconvertedsignal, and thus, the RX’s noise figure (NF). In contrast to con-ventional wireless communication systems, there is no specifichigh power RF interference in the RX band of 80–92 GHz. As-sumingthehighestneighboringblockingsignalisnolargerthanthe expected received RF signal of dBm (whereGHz), the noise power at an offset frequency of 100 MHz introduced by the LO phase noise is calculated asMHz . In order to ensure thatthe LO phase noise contributes negligible noise to the RX atthe frequency offset of 100 MHz, based on assumed blockingsignal level of 62.5 dBm, the LO phase noise needs to bedBc Hz.  D. Dicke Switch Insertion Loss The insertion loss of the Dicke switch at the RX’s input di-rectly degrades the RX responsivity and NEP. In order to meetthe 1K NETD requirement, the insertion loss should be keptlower than 3 dB for our designed RX. However, on-chip SPDTswitchin65nmCMOSexhibitsaninsertionlossof4–5dB[18].Therefore, in this prototype, to maximize the power detectionperformance of the RX in 65 nm CMOS, Dicke switch modu-lation is emulated off-chip to compensate for the gain variationand improve the RX sensitivity.IV. PMMW I MAGING R ECEIVER F RONT -E ND  A. Passive Components Passives are considered to be the key components inthe MMW IC design. Transmission lines (T-lines) providebetter model accuracy than inductors due to the well-definedground planes. However, the use of T-lines results in a notice-able increase in chip area. Slow-wave coplanar waveguides(SW-CPWs) are thus used as part of the on-chip matching  ZHOU et al. : A W-BAND CMOS RECEIVER CHIPSET FOR MILLIMETER-WAVE RADIOMETER SYSTEMS 381 Fig. 3. SW-CPW and microstrip comparison. (a) Transmission loss. (b) Q  factor. (c) FOM. networks in our design [29], [30]. The top two metals areshunted together and used for the signal line. The coplanargrounds are shunted with all metal layers M3–M7, since thelowest two are used for floating shield. To ensure that the twocoplanar ground planes are at the same potential, underpassesusing metal layers M3–M5 are used. These underpasses useminimum width allowed by the technology in order to suppressthe induced current flow in the direction of signal propagation.Metal density requirement is met by efficient use of all metallayers in the ground plane, as for middle conductor, the require-ment is met by the periodic underpasses.Since the characteristic impedance is close to 50 , inorder for a grounded CPW to achieve such high characteristicimpedance, the ratio must decrease ( : width,: spacing). A grounded CPW (GCPW) with m andm canachievethischaracteristicimpedance.AGCPWwith such a wide spacing is roughly equivalent to a microstripwith M1 ground shield. The width and spacing of SW-CPW are10 m and 20 m, respectively. A microstrip with mwith M1 ground shield is used for comparison. The EM simu-lated result includes skin effect as well as substrate loss. In theEM simulation environment, substrate loss is set to 10 cm.In addition, the SiO dielectric loss is also taken into accountin the EM simulation with loss tangent of 0.01. Microstrip linesachieve losses of 1.2 dB/mm at 30 GHz and around 1.8 dB/mmat 90 GHz, as shown in Fig. 3(a), which is mainly attributedto the shorter line width. The SW-CPW achieves 0.9 dB/mmattenuation at 90 GHz. Moreover, the high relative dielectricpermittivity of 10 achieved by the SW-CPW compared to just 4.5 for the microstrip line means that an effectively longelectrical length can be realized using a shorter physical length.Fig. 3(b) also compares the quality factors (), as defined in[31], of the microstrip line and the SW-CPW. At 90 GHz, anSW-CPW achieves a of 26.3 compared to only 8.9 achievedby a microstrip line. Note that the improvement in overallof the SW-CPW compared to a microstrip line is a result of agiven line-to-ground distance and shorter line width. Finally,an appropriate figure-of-merit (FOM) for the T-line’s loss isor (dB/rad), which takes into account the wavelengthdue to increased permittivity. The major benefit of slow-wavestructure is evidenced in Fig. 3(c). It shows that for the samephase delay, the SW-CPW has lower loss than a microstrip line.  B. LNA The LNA schematic is shown in Fig. 4(a), which consistsof a five-stage SW-CPW-based CS amplifier (similar to [32]).Cascode topology is known to provide high gain and goodinput-output isolation for stability. However, it begins to loseits high gain advantage for operation frequencies close to thetransistor’s , due to relatively large parasitic capacitance atthe drain node of the CS transistor (intermediate node), andthe substrate resistance of the common gate (CG) transistor.In addition, insufficient voltage headroom limits the dynamicrange of cascode topology compared to CS structure. Althoughadding an inductor between the CS and CG stages [33], [34]can boost high-frequency gain by resonating out the parasiticcapacitors, the low supply voltage in 65 nm CMOS still limitsthe cascode topology to achieve high gain and good linearityin W-band [35]. In addition, this inter-stage inductor leadsto complex layout and larger chip area. This is because thedrain of CS and source of CG stage in a cascode topologyare normally shared to achieve a compact layout. In spite of the poor isolation between input and output of CS topology, itis possible to achieve good gain and noise figure using a CSLNA by proper design and careful layout of active and passiveelements.The matching is performed using SW-CPWs, where they areused as series and shunt stubs. The width and spacing of theSW-CPW are 10 m and 20 m, respectively, to achieve a char-acteristic impedance of 50 . The alternate floating shields areimplemented using the two lowest metal layers each with 1 mwidth. In [31], it is shown that in matching networks, T-linesstoremostlymagnetic energy.Hence,theT-line’slossis mostlyattributed to . At 90 GHz, a CS stage is conditionally stable.This means that the input and output matching networks of eachstage have to be carefully designed to avoid stability issue [36].Hence, the CS-based LNA design involves a trade-off betweengain, stability and noise figure. Fig. 4(b) shows how the inputmatching is performed on the Smith chart. Input stability circle,available gain and noise figure circles are all overlaid on thesame Smith chart. Starting from 50 input, the pad and MIM  382 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011 (a)(b)Fig. 4. (a) Five-stage LNA schematic. (b) LNA matching curve. capacitormovetheimpedancetopoint and .Thematchingis finalized with series and shunt T-line (point ). The de-sign does not intend for optimum noise figure, as it would de-grade gain and input matching. The output matching circuit isdesigned in a similar fashion, in which power gain circles to-gether with the output stability circle are used to determine theoptimum matching point.The five-stage LNA takes advantage of accurate modelingof passive components and uses equally sized transistors to re-duce the modeling inaccuracy in W-band. Both the input andoutput ports are matched to 50 with pad’s parasitic absorbedas part of the design for both direct and in situ probing. Eachtransistor is biased separately to balance between noise figureandgain.Smallsourcedegenerationinductorsaround20pHareintroduced to model the non-ideal connection to the mesh-typeground plane. RC  networks at the supply line and gate terminalof the transistor [shown in Fig. 4(a)] are included to ensure low-frequencystabilityoftheamplifier.Theypreventresonancesbe-tweenRFshuntcapacitanceandtheinductanceofthedcprobes. Fig. 5. Schematic of (a) mixer and (b) zero-IF amplifier. C. Mixer and Zero-IF Amplifier  The mixer’s schematic is shown in Fig. 5(a). Since the IFfrequency band (0.1–6 GHz) is far from the LO frequency(90 GHz), the LO feedthrough can be suppressed at the mixer’soutput, therefore, a single-balanced mixer is chosen for betternoise performance. A SW-CPW T-line is inserted between thedrain of and the common source node of to increasethe conversion gain of the mixer overthe wide 6 GHz frequencyrange. A balun converts single-ended LO from the tripler toa differential signal. The simulated in-band (80–92GHz) in-sertion loss of the on-chip balun is less than 2 dB. In order tominimize the gain and phase mismatch, the balun is placedcloseto themixerin thelayout. Themixer’soutput is connectedto the input of the first-stage zero-IF amplifier. Fig. 5(b) showsthe schematic of the amplifier. The input of the amplifier isAC-coupled with a low cut-off frequency at 100 MHz to re-move the DC offset voltage from the mixer. In order to achievethe required 6 GHz bandwidth without using area inefficientinductors, an active feedback amplifier is utilized. Two activefeedback amplifiers are cascaded to achieve 20 dB gain overthe 6 GHz bandwidth [37]. To reduce the input-referred noiseof the amplifier, a third-order gain stage with higher gainbandwidth product is chosen to reduce the number of stages totwo [Fig. 5(b)].
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